XRT86VL32IB datasheet(41/155 Pages) EXAR

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XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 22: DMA 1 (READ) CONFIGURATION REGISTER (D1RCR)

HEX ADDRESS: 0Xn119

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

7-6

Reserved

DMA1 RST

R/W

DMA_1 Reset

This bit resets the Receive DMA (Read) Channel 1

0 = Normal operation.

1 = A zero to one transition resets the Receive DMA (Read) channel 1.

DMA1 ENB

R/W

DMA1_ENB

This bit enables the Receive DMA_1 (Read) interface. After a receive

DMA is enabled, DMA transfers are only requested when the receive

cell buffer contains a complete message or cell.

The DMA read channel is used by the T1 Framer to transfer data from

the HDLC buffers within the T1 Framer to external memory. The DMA

Read cycle starts by T1 Framer asserting the DMA Request (REQ1)

‘low’, then the external DMA controller should drive the DMA Acknowl-

edge (ACK1) ‘low’ to indicate that it is ready to receive the data. The

T1 Framer should place new data on the Microprocessor data bus

each time the Read Signal is Strobed low if the RD is configured as a

Read Strobe. If RD is configured as a direction signal, then the T1

Framer would place new data on the Microprocessor data bus each

time the Write Signal (WR) is Strobed low.

0 = Disables the DMA_1 (Read) interface

1 = Enables the DMA_1 (Read) interface

RD TYPE

R/W

READ Type Select

This bit selects the function of the RD signal.

0 = RD functions as a Read Strobe signal

1 = RD acts as a direction signal (indicates whether the current bus

cycle is a read or write operation), and WR works as a data strobe.

4 - 3 Reserved

Reserved

DMA1_CHAN(2)

R/W

Channel Select

These three bits select which T1 channel within the chip uses the

Receive DMA_1 (Read) interface.

000 = Channel 0

001 = Reserved

001 = Channel 2

011 = Reserved

1xx = Reserved

DMA1_CHAN(1)

R/W

DMA1_CHAN(0)

R/W

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