Data Sheet

AD5121/AD5141

SPECIFICATIONS

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Rev. E | 7 of 30

Table 3. (Continued)

Parameter

Symbol

Test Conditions/Comments

Min

Typ1

Max

Unit

RAB = 10 kΩ

3

MHz

RAB = 100 kΩ

0.43

MHz

Total Harmonic Distortion

THD

VDD/VSS = ±2.5 V, VA = 1 V rms,

VB = 0 V, f = 1 kHz

RAB = 10 kΩ

−80

dB

RAB = 100 kΩ

−90

dB

Resistor Noise Density

eN_WB

Code = half scale, TA = 25°C,

f = 10 kHz

RAB = 10 kΩ

7

nV/√Hz

RAB = 100 kΩ

20

nV/√Hz

VW Settling Time

tS

VA = 5 V, VB = 0 V, from zero scale

to full scale, ±0.5 LSB error band

RAB = 10 kΩ

2

µs

RAB = 100 kΩ

12

µs

Endurance10

TA = 25°C

1

Mcycles

100

kcycles

Data Retention11, 12

50

Years

1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.

2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.

3 Guaranteed by design and characterization, not subject to production test.

4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions.

5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground

referenced bipolar signal adjustment.

6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.

7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.

8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).

9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V.

10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.

11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates

with junction temperature in the Flash/EE memory.

12 50 years applies to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years.

INTERFACE TIMING SPECIFICATIONS

VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 4. SPI Interface

Parameter1

Test Conditions/Comments

Min

Typ

Max

Unit

Description

t1

VLOGIC > 1.8 V

20

ns

SCLK cycle time

VLOGIC = 1.8 V

30

ns

t2

VLOGIC > 1.8 V

10

ns

SCLK high time

VLOGIC = 1.8 V

15

ns

t3

VLOGIC > 1.8 V

10

ns

SCLK low time

VLOGIC = 1.8 V

15

ns

t4

10

ns

SYNC-to-SCLK falling edge setup time

t5

5

ns

Data setup time