AD5124 datasheet(25/30 Pages) AD

25 / 30 page

Data Sheet

AD5121/AD5141

THEORY OF OPERATION

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Rev. E | 25 of 30

Table 14. Address Bits

Potentiometer Mode

Linear Gain Setting Mode

Stored RDAC Memory

Input Register

RDAC Register

Input Register

RDAC Register

All channels

Not applicable

RDAC

RWB

RDAC/RWB

Not applicable

RAW

Not applicable

RAW

Not applicable

MSB tolerance

Not applicable

LSB tolerance

1 X= don't care.

Table 15. Control Register Bit Descriptions

Bit Name

Description

RDAC register write protect

0 = wiper position frozen to value in EEPROM memory

1 = allows update of wiper position through digital interface (default)

EEPROM program enable

0 = EEPROM program disabled

1 = enables device for EEPROM program (default)

Linear setting mode/potentiometer mode

0 = potentiometer mode (default)

1 = linear gain setting mode

Burst mode (I2C only)

0 = disabled (default)

1 = enabled (no disable after stop or repeat start condition)

Input Register

The AD5121/AD5141 include one input register per RDAC register.

This register allows preloading of the value for the associated

RDAC register.

This feature allows a synchronous and asynchronous update of one

or all the RDAC registers at the same time.

These registers can be written to using Command 2 and read back

from using Command 3 (see Table 13).

The transfer from the input register to the RDAC register is done

asynchronously by the LRDAC pin or synchronously by Command

8 (see Table 13).

If new data is loaded in an RDAC register, this RDAC register

automatically overwrites the associated input register.

Linear Gain Setting Mode

The proprietary architecture of the AD5121/AD5141 allows the in-

dependent control of each string resistor, RAW and RWB. To enable

this feature, use Command 16 (see Table 13) to set Bit D2 of the

control register (see Table 15).

This mode of operation can control the potentiometer as two inde-

pendent rheostats connected at a single point, W terminal, as

opposed to potentiometer mode where each resistor is complemen-

tary, RAW = RAB − RWB.

This feature enables a second input and an RDAC register per

channel, as shown in Table 13; however, the actual RDAC contents

remain unchanged. The same operations are valid for potentiome-

ter and linear gain setting modes.

If the INDEP pin is pulled high, the device powers up in linear gain

setting mode and loads the values stored in the associated memory

locations for each channel (see Table 14). The INDEP pin and D2

bit are connected internally to a logic OR gate, if any or both are 1,

the devices cannot operate in potentiometer mode.

Low Wiper Resistance Feature

The AD5121/AD5141 include two commands to reduce the wiper

resistance between the terminals when they achieve full scale or

zero scale. These extra positions are called bottom scale, BS, and

top scale, TS. The resistance between Terminal A and Terminal

W at top scale is specified as RTS. Similarly, the bottom scale

resistance between Terminal B and Terminal W is specified as RBS.

The contents of the RDAC registers are unchanged by entering

in these positions. There are two ways to exit from top scale and

bottom scale: by using Command 12 or Command 13 (see Table

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