AD5124 datasheet(29/30 Pages) AD

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Data Sheet

AD5121/AD5141

THEORY OF OPERATION

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Rev. E | 29 of 30

Table 20. End-to-End Resistance Tolerance Bytes

Memory Map Address

Data Byte

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0x02

Sign

0x03

2−1

2−2

2−3

2−4

2−5

2−6

2−7

2−8

TERMINAL VOLTAGE OPERATING RANGE

The AD5121/AD5141 are designed with internal ESD diodes for

protection. These diodes also set the voltage boundary of the

terminal operating voltages. Positive signals present on Terminal

A, Terminal B, or Terminal W that exceed VDD are clamped by the

forward-biased diode. There is no polarity constraint between VA,

VW, and VB, but they cannot be higher than VDD or lower than VSS.

Figure 48. Maximum Terminal Voltages Set by VDD and VSS

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at Termi-

nal A, Terminal B, and Terminal W (see Figure 48), it is important to

power up VDD first before applying any voltage to Terminal A, Termi-

nal B, and Terminal W. Otherwise, the diode is forward-biased such

that VDD is powered unintentionally. The ideal power-up sequence

is VSS, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order

of powering VA, VB, VW, and digital inputs is not important as long

as they are powered after VSS, VDD, and VLOGIC. Regardless of the

power-up sequence and the ramp rates of the power supplies, once

VLOGIC is powered, the power-on preset activates, which restores

EEPROM values to the RDAC registers.

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to use a compact, minimum lead

length layout design. Ensure that the leads to the input are as

direct as possible with a minimum conductor length. Ground paths

should have low resistance and low inductance. It is also good

practice to bypass the power supplies with quality capacitors. Apply

low equivalent series resistance (ESR) 1 µF to 10 µF tantalum

or electrolytic capacitors at the supplies to minimize any transient

disturbance and to filter low frequency ripple. Figure 49 illustrates

the basic supply bypassing configuration for the AD5121/AD5141.

Figure 49. Power Supply Bypassing

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