AD5124 datasheet(27/30 Pages) AD

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Data Sheet

AD5121/AD5141

THEORY OF OPERATION

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Rev. E | 27 of 30

EEPROM OR RDAC REGISTER PROTECTION

The EEPROM and RDAC registers can be protected by disabling

any update to these registers. This can be done by using software

or by using hardware. If these registers are protected by software,

set Bit D0 and/or Bit D1 (see Table 15), which protects the RDAC

and EEPROM registers independently.

If the registers are protected by hardware, pull the WP pin low. If

the WP pin is pulled low when the device is executing a command,

the protection is not enabled until the command is completed.

When RDAC is protected, the only operation allowed is to copy the

EEPROM into the RDAC register.

LOAD RDAC INPUT REGISTER (LRDAC)

LRDAC software or hardware transfers data from the input register

to the RDAC register (and therefore updates the wiper position).

By default, the input register has the same value as the RDAC

using Command 2 is updated.

Software LRDAC, Command 8, allows updating of a single RDAC

synchronous update.

The hardware LRDAC is completely asynchronous and copies the

content of all the input registers into the associated RDAC registers.

If a command is executed, to avoid data corruption, any transition in

the LRDAC pin is ignored by the device.

INDEP PIN

If the INDEP pin is pulled high at power-up, the device operates in

linear gain setting mode, loading each string resistor, RAW and RWB,

with the value stored into the EEPROM (see Table 14). If the pin is

pulled low, the device powers up in potentiometer mode.

The INDEP pin and the D2 bit are connected internally to a logic

OR gate, if any or both are 1, the device cannot operate in

potentiometer mode (see Table 15).

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices, Inc., uses a pro-

prietary RDAC segmentation architecture for all the digital potenti-

ometers. In particular, the AD5121/AD5141 employ a three‑stage

segmentation approach, as shown in Figure 45. The AD5121/

AD5141 wiper switch is designed with the transmission gate CMOS

topology and with the gate voltage derived from VDD and VSS.

Figure 45. AD5121/AD5141 Simplified RDAC Circuit

Top Scale/Bottom Scale Architecture

In addition, the AD5121/AD5141 include new positions to reduce

the resistance between terminals. These positions are called bot-

tom scale and top scale. At bottom scale, the typical wiper resist-

ance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ). At top scale,

the resistance between Terminal A and Terminal W is decreased by

1 LSB, and the total resistance is reduced to 60 Ω (RAB = 100 kΩ).

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation—±8% Resistor Tolerance

The AD5121/AD5141 operate in rheostat mode when only two

terminals are used as a variable resistor. The unused terminal can

be floating, or it can be tied to Terminal W, as shown in Figure 46.

Figure 46. Rheostat Mode Configuration

The nominal resistance between Terminal A and Terminal B, RAB,

is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by the

wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded

to select one of the 128/256 possible wiper settings. The general

equations for determining the digitally programmed output resist-

ance between Terminal W and Terminal B are

AD5121:

RWBD = D128×RAB+RW From 0x00 to 0x7F (1)

AD5141:

RWBD = D256×RAB+RW From 0x00 to 0xFF (2)

where:

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