Data Sheet

AD5121/AD5141

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. E | 12 of 30

Figure 7. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GND

Ground Pin, Logic Ground Reference.

2

A

Terminal A of RDAC. VSS ≤ VA ≤ VDD.

3

W

Wiper terminal of RDAC. VSS ≤ VW ≤ VDD.

4

B

Terminal B of RDAC. VSS ≤ VB ≤ VDD.

5

VSS

Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

6

SYNC/ADDR0

Programmable Address (ADDR0) for Multiple Package Decoding, DIS = 1.

Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the RDAC register, DIS = 0.

7

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low. If this pin is not used, tie RESET to

VLOGIC.

8

DIS

Digital Interface Select (SPI/I2C Select). This pin cannot be left floating.

SPI when DIS = 0 (GND).

I2C when DIS = 1 (VLOGIC).

9

VDD

Positive Power Supply. Decouple this pin with 0.1µF ceramic capacitors and 10 µF capacitors.

10

VLOGIC

Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

11

SCLK/SCL

SPI Serial Clock Line (SCLK). Data is clocked in at logic low transition.

I2C Serial Clock Line (SCL). Data is clocked in at logic low transition.

12

SDI/SDA

Serial Data Input/Output (SDA), when DIS = 1.

Serial Data Input (SDI), when DIS = 0.

13

WP

Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM contents, except when reloading the content of

the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used, tie WP to VLOGIC

14

SDO/ADDR1

Programmable Address (ADDR1) for Multiple Package Decoding, when DIS = 1.

Serial Data Output (SDO). This is an open-drain output pin, and it needs an external pull-up resistor when DIS = 0.

15

INDEP

Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associate memory location. If INDEP is enabled, it cannot be

disabled by the software.

16

LRDAC

Load RDAC. Transfers the contents of the input register to the RDAC register. This allows asynchronous RDAC update. LRDAC is activated

low. If this pin is not used, tie LRDAC to VLOGIC.

EPAD

Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended

that the pad be thermally connected to a copper plane for enhanced thermal performance.