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Data Sheet

AD5121/AD5141

THEORY OF OPERATION

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Rev. E | 20 of 30

SERIAL DATA DIGITAL INTERFACE

SELECTION, DIS

The AD5121/AD5141 LFSCP provides the flexibility of a selectable

interface. When the digital interface select (DIS) pin is tied low, the

SPI mode is engaged. When the DIS pin is tied high, the I2C mode

is engaged.

SPI SERIAL DATA INTERFACE

The AD5121/AD5141 contain a 4-wire, SPI-compatible digital inter-

face (SDI, SYNC, SDO, and SCLK). The write sequence begins by

bringing the SYNC line low. The SYNC pin must be held low until

the complete data-word is loaded from the SDI pin. Data is loaded

in at the SCLK falling edge transition, as shown in Figure 4. When

SYNC returns high, the serial data-word is decoded according to

the instructions in Table 13.

The AD5121/AD5141 do not require a continuous SCLK when

SYNC is high. To minimize power consumption in the digital input

buffers when the device is enabled, operate all serial interface pins

close to the VLOGIC supply rails.

SYNC Interruption

In a standalone write sequence for the AD5121/AD5141, the SYNC

line is kept low for 16 falling edges of SCLK, and the instruction

is decoded when SYNC is pulled high. However, if the SYNC line

is kept low for less than 16 falling edges of SCLK, the input shift

invalid.

SDO Pin

The serial data output pin (SDO) serves two purposes: to read back

the contents of the control, EEPROM, RDAC, and input registers

using Command 3 (see Table 11 and Table 13), and to connect the

AD5121/AD5141 to daisy-chain mode.

The SDO pin contains an internal open-drain output that needs an

external pull-up resistor. The SDO pin is enabled when SYNC is

pulled low, and the data is clocked out of SDO on the rising edge of

SCLK.

Daisy-Chain Connection

Daisy-chaining minimizes the number of port pins required from the

controlling IC. As shown in Figure 40, the SDO pin of one package

must be tied to the SDI pin of the next package. The clock period

may need to be increased because of the propagation delay of

the line between subsequent devices. When two AD5121/AD5141

devices are daisy chained, 32 bits of data are required. The first

16 bits assigned to U2, and the second 16 bits assigned to U1, as

shown in Figure 41. Keep the SYNC pin low until all 32 bits are

clocked into their respective serial registers. The SYNC pin is then

pulled high to complete the operation. A typical connection is shown

in Figure 40.

To prevent data from mislocking (for example, due to noise) the

device includes an internal counter, if the clock falling edges count

is not a multiple of 8, the device ignores the command. A valid clock

count is 16, 24, or 32. The counter resets when SYNC returns high.

Figure 40. Daisy-Chain Configuration

Figure 41. Daisy-Chain Diagram

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