Data Sheet

AD5121/AD5141

SPECIFICATIONS

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Rev. E | 9 of 30

Table 6. Control Pins

Parameter

Min

Typ

Max

Unit

Description

t1

1

µs

End command to LRDAC falling edge

t2

50

ns

Minimum LRDAC low time

t3

0.1

10

µs

RESET low time

tEEPROM_PROGRAM1

15

50

ms

Memory program time (not shown in Figure 6)

tEEPROM_READBACK

7

30

µs

Memory readback time (not shown in Figure 6)

tPOWER_UP2

75

µs

Power-on EEPROM restore time (not shown in Figure 6)

tRESET

30

µs

Reset EEPROM restore time (not shown in Figure 6)

1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.

2 Maximum time after VDD − VSS is equal to 2.3 V.

SHIFT REGISTER AND TIMING DIAGRAMS

Figure 2. Input Shift Register Contents

Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence)

Figure 4. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1

Figure 5. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0