AD8152

Data Sheet

Rev. B | Page 8 of 25

ABSOLUTE MAXIMUM RATINGS

Table 12.

Parameter

Rating

VCC to VEE

3.7 V

VTTI

VCC + 0.6 V

VTTO

VCC + 0.6 V

Internal Power Dissipation1

Input Voltage

VCC + 0.6 V

Differential Input Voltage

1.7 V

Logic Input Voltage

VEE − 0.3 V < input voltage (VIN) <

VCC + 0.6 V

Storage Temperature Range

−65°C to +125°C

Lead Temperature

300°C

Maximum Junction

Temperature

175°C

1

Specification is for the device in free air (TA = 25°C): θJA = 9.2°C/W at still air.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8152

is limited by the associated rise in junction temperature. The

maximum safe junction temperature for plastic encapsulated

devices is determined by the glass transition temperature of the

plastic, approximately 150°C. Temporarily exceeding this limit

may cause a shift in parametric performance due to a change in

the stresses exerted on the die by the package. Exceeding a junction

temperature of 175°C for an extended period can result in device

failure. To ensure proper operation, it is necessary to observe

the maximum power derating curves shown in Figure 7.

16

0

2

4

6

8

10

12

14

0

10

20

30

40

50

60

70

80

90

AMBIENT TEMPERATURE (°C)

400 LFPM

200 LFPM

STILL AIR

Figure 7. Maximum Power Dissipation vs. Ambient Temperature

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required.

θJA is the thermal resistance ambient environment and θJC_TOP is

the thermal resistance to the top of the package.

Thermal resistance values specified in Table 13 are simulated

based on JEDEC specifications (unless specified otherwise) and

must be used in compliance with JESD51-12.

Table 13. Thermal Resistance

PackageType1

θJA

θJC_TOP2

Unit

BP-256-3

9.2

0.5

°C/W

1

Using enhanced heat removal (PCB, heat sink, and airflow) technique

improves thermal resistance values.

2

For the θJC_TOP test, 100 μm thermal insulation material (TIM) is used. TIM is

assumed to have 3.6 W/mK.

ESD CAUTION