AD8152 datasheet(19/25 Pages) AD

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Data Sheet

AD8152

Rev. B | Page 19 of 25

THEORY OF OPERATION

The AD8152 control interface receives and stores the desired

connection matrix and output levels for the 34 input and 34

output signal pairs. The interface consists of 34 rows of double-

rank 6-bit latches, one for each output. The 6-bit data-word stored

in these latches indicates to which (if any) of the 34 inputs the

output is connected, as well as the full-scale output current.

One output at a time can be preprogrammed by addressing the

output and writing the desired connection data or output current

into the first rank of latches. This process can be repeated until

all desired output changes are preprogrammed. All output connec-

tions can then be programmed simultaneously by passing the

data from the first rank of latches into the second rank. The output

connections always reflect the data programmed into the second

rank of latches and do not change until the first rank of data is

passed into the second rank.

If necessary for system verification, the data in the second rank

of latches can be read back from the control interface.

At any time, a reset pulse can be applied to the control interface

to globally reset the appropriate second rank data bits, disabling

all 34 signal output pairs and resetting the output currents. To

facilitate multiple chip address decoding, there is a chip select

pin. All logic signals except the reset pulse are ignored, unless

the chip select pin is active. The chip select pin disables only the

control logic interface and does not change the operation of the

signal matrix. The chip select pin does not power down any of

the latches thus, any data programmed in the latches is preserved.

All control pins are level sensitive, not edge triggered.

CONTROL PIN DESCRIPTION

A0 to A6 Inputs

A0 to A6 output address pins. The binary encoded address

applied to the lower A5 to A0 input pins determines which of

the 34 outputs is being programmed (or being read back). The

most significant bit, A6, determines whether the data pins contain

information for the connection register bank or the output level

simultaneously programs data into all of the outputs.

D5 to D0 Inputs/Outputs

D0 to D5 input configuration or output level data pins. In write

mode, when the bank selection bit A6 is low, the binary encoded

data applied to Pin D5 to Pin D0 determine which of the 34

inputs is to be connected to the output specified with the A5 pin

to A0 pin. The most significant bit is D5 and the least significant

bit is D0. To disable an output completely, the input address D5

to D0 = 111111 must be written into the input configuration

bank at the desired output address.

In write mode, when the bank selection bit, A6, is high, the

binary encoded data applied to Pin D3 to Pin D0 indicate the

output current level to be used for the output specified with the

A5 pin to A0 pin. The reset default is 0111 for 16 mA. Each LSB

is 2 mA.

In readback mode, Pin D5 to Pin D0 are low impedance outputs

indicating the data-word stored in the second rank for the output

specified with the A5 pin and A0 pin and the bank specified

with the A6 bit. The readback drivers are designed to drive high

impedances only. Therefore, external drivers connected to D5 to

D0 must be disabled during readback mode.

WE Input

WE is the first rank write enable pin. Forcing this pin to logic

low allows the data on Pin D5 to Pin D0 to be stored in the first

rank latch for the output specified by Pin A6 to Pin A0. The WE

pin must be returned to a logic high state after a write cycle to

avoid overwriting the first rank data.

UPDATE Input

UPDATE is the second rank write enable pin. Forcing this pin

to logic low allows the data stored in all 34 first rank latches (in

both banks) to be transferred to the second rank latches. The

signal connection matrix is reprogrammed when the second

rank data and levels are changed. UPDATE is a global pin,

transferring all 34 rows of data at once. It is not necessary to

program the address pins. After initial power-up of the device,

the first rank data is undefined. It is recommended to preprogram

all 17 outputs before performing the first update cycle.

RE Input

RE is the second rank read enable pin. Forcing this pin to logic low

enables the output drivers on the bidirectional D5 pin to D0 pin,

entering the readback mode of operation. By selecting an output

address with the A6 pin to A0 pin and forcing RE to logic low, the

6-bit data stored in the second rank latch for that output address is

written to the D5 pin to D0 pin. It is not recommended to write

data to the D5 pin to D0 pin externally while in readback mode.

The RE pin is a higher priority pin than the WE pin. Therefore,

first rank programming is not possible while in readback mode.

CS Input

CS is the chip select pin. This pin must be forced to logic low to

program or receive data from the logic interface, with the

exception of the RESET pin, described in the RESET Input

section. This pin has no effect on the signal pairs and does not

alter any of the stored control data.

RESET Input

RESET is the global output disable pin. Forcing the RESET pin

to logic low disables all outputs and, regardless of the state of any

other pins, sets both ranks of all 34 input connection latches. This

logic low immediately disables the 34 output signal pairs in the

matrix. The output level information is also changed. It is

necessary to momentarily hold RESET at a logic low state when

powering up the AD8152 to avoid random internal contention

where multiple inputs may be connected to one output. The RESET

pin is not gated by the state of the chip select pin, CS.

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