AD8152 datasheet(20/25 Pages) AD

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AD8152

Data Sheet

Rev. B | Page 20 of 25

Control Interface Levels

The AD8152 control interface shares the data path supply pins,

VCC and VEE. The potential between the positive logic supply

(VCC) and the negative supply (VEE) must be at least 2.25 V

and no more than 3.63 V. Regardless of the supply, the logic

threshold is approximately one-half the supply range, allowing the

interface to be used with most LVCMOS and LVTTL logic

drivers.

Output Addressing

The AD8152 is programmed using a memory interface module,

with parallel address and data buses. Six bits, [A5:A0], are used

to address the outputs (see Table 5). By setting the decimal

value of these address bits to a value from 0 to 33 inclusive, one

of the 34 outputs is uniquely addressed.

One additional decimal code, 63 (all 1s), is used for the

broadcast mode. If this address is selected, then all outputs

receive the same programming. The remaining addresses in the

to Decimal Code 66 inclusive.

Connection and Output Current Programming

A seventh address bit (A6) determines which of two types of

programming is selected. If A6 = 0, connection matrix

programming (connecting an input to an output) is selected.

If A6 = 1, output current programming is selected.

Output Current Programming

A current source in each output can be digitally programmed to

any one of 16 different current levels. Changing these current

levels changes the amplitude of the output swing that is developed

across the internal 50 Ω termination resistors.

To program the current for a particular output, the address is

set on Control Pin A5 to Control Pin A0 (Decimal Code 00 to

Decimal Code 33), while A6 is set to 1. The four LSBs of the data

address, [D3:D0], are then used to select one of the 16 output

current levels. D4 and D5 assume the don’t care value for output

current programming (see Table 5).

To program all outputs to the same current level, set the address

bus, A5 to A0, to broadcast Decimal Code 63 with A6 = 1.

Address Pin D3 to Address Pin D0 then program all output

currents to the same level.

When the current code is set to 0000, a minimum current level

of 2 mA is obtained. For any other code, the current can be

calculated by (current code) × 2 mA + 2 mA. Refer to Table 5

for current code values. For example, 16 mA can be programmed

by Decimal Code 7. This value is 7 × 2 mA + 2 mA = 16 mA.

Using the Data Bus

After determining which output to program (or broadcast to all

outputs) and which type of programming (connection/output

current) to use, the data bits, [D5:D0], then further define the

programming action.

If connection programming (A6 = 0) is selected, the data bits

select the input that is to be connected to the addressed output.

If the broadcast address is selected, the data bits select the input

that is connected to all 34 outputs (see Table 4).

A disable code (Bits[D5:D0] = 63 decimal value, or all 1s) disables

(and powers down) the particular output that is addressed. A

broadcast can be put into effect by setting Decimal Code 63 on

both the address bus and the data bus along with A6 = 0.

Several single-ended logic input pins control the register loading

associated with the address and data buses described in the

Using the Data Bus section. The control functions are tabulated

in Table 6

There are dual ranks of registers for the data that programs the

AD8152. The first rank registers accumulate the data for the

various outputs as they are being programmed one by one. The

second rank registers actually control the functions of the device.

The RESET signal resets the connection matrix, disables all

outputs, and sets all of the output currents to a default condition at

Decimal Code 7. This signal sets the output current to a nominal

value of 16 mA. The data in the first rank latches is also reset by

the assertion of RESET.

The CS signal enables the control interface. If several devices

are used in a system with the other control signals bussed, the

CS signal can select an individual device to change the

programming.

The WE signal enables writing data to the first rank registers.

This data does not immediately affect the features of the

AD8152.

The UPDATE signal transfers the data from the first rank

registers to the second rank registers. After the UPDATE signal

is asserted, the data actively controls the AD8152 functions.

The second rank registers can be read back through the data bus.

The output is addressed on Bits[A5:A0] and the connection or

current is selected via A6. Asserting RE causes the second rank

data to appear on the data bus. The RE function dominates over

WE if both are asserted at the same time. Broadcast readback is

not permitted.

Some typical programming waveforms for the control signals

are provided in Figure 34.

VALID ADDRESS INPUT

VALID DATA INPUT

VALID ADDRESS INPUT

VALID DATA INPUT

A6 TO A0

D5 TO D0

UPDATE

Figure 34. Programming Waveforms

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