Data Sheet

LTC2672

SPECIFICATIONS

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Rev. B | 7 of 27

solder/via all GND and REFLO pins as well as the exposed pad (LFCSP package only) to a solid GND plane and set VDDx as low as practicable for each channel to reduce

power dissipation in the device.

7 Internal reference mode. The load is 15 Ω (200 mA range) or 800 Ω (3.125 mA range) terminated to GND.

8 DAC to DAC crosstalk is the glitch that appears at the output of one DAC because of a 100 mA to 200 mA step change in an adjacent DAC channel. The measured DAC is

at midscale (100 mA output current) in the 200 mA span range, with the internal reference, VDDx = 5 V, V− = −3.3 V.

9 The temperature coefficient is calculated by first computing the ratio of the maximum change in the output voltage to the nominal output voltage, and then dividing the ratio

by the specified temperature range.

10 Guaranteed by design and not production tested.

11 Stresses beyond those listed for extended periods can cause permanent damage to the device or affect device reliability and lifetime.

12 Single channel at a specified output.

13 VCC = IOVCC = 5 V, VDDx = 5 V, V− = −3.3 V.

14 Digital inputs are at 0 V or IOVCC.

TIMING CHARACTERISTICS

All specifications apply over the full operating TJ range. Digital input low and high voltages are 0 V and IOVCC, respectively.

Table 2. 2.85 V ≤ VCC ≤ 5.5 V and 2.85 V ≤ IOVCC ≤ VCC

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

t1

SDI valid to SCK setup

6

ns

t2

SDI valid to SCK hold

6

ns

t3

SCK high time

9

ns

t4

SCK low time

9

ns

t5

CS/LD pulse width

10

ns

t6

LSB SCK high to CS/LD high

19

ns

t7

CS/LD low to SCK high

7

ns

t8

SDO propagation delay from SCK falling edge, CLOAD = 10 pF, 4.5 V < IOVCC < VCC

20

ns

SDO propagation delay from SCK falling edge, CLOAD = 10 pF, 2.85 V < IOVCC < 4.5 V

30

ns

t9

CLR pulse width

20

ns

t10

CS/LD high to SCK positive edge

7

ns

t11

LDAC pulse width

15

ns

t12

CS/LD high to LDAC high or low transition

15

ns

fSCK

SCK frequency

50

MHz

t13

TGP high time1

1

μs

t14

TGP low time1

1

μs

1 Guaranteed by design and not production tested.

Table 3. 2.85 V ≤ VCC ≤ 5.5 V and 1.71 V ≤ IOVCC ≤ 2.85 V

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

t1

SDI valid to SCK setup

7

ns

t2

SDI valid to SCK hold

7

ns

t3

SCK high time

30

ns

t4

SCK low time

30

ns

t5

CS/LD pulse width

15

ns

t6

LSB SCK high to CS/LD high

19

ns

t7

CS/LD low to SCK high

7

ns

t8

SDO propagation delay from SCK falling edge, CLOAD = 10 pF

60

ns

t9

CLR pulse width

30

ns

t10

CS/LD high to SCK positive edge

7

ns

t11

LDAC pulse width

15

ns

t12

CS/LD high to LDAC high or low transition

15

ns