LTC2672 datasheet(9/27 Pages) AD

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Data Sheet

LTC2672

ABSOLUTE MAXIMUM RATINGS

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Rev. B | 9 of 27

Table 4.

Parameter

Rating

VCC to GND

−0.3 V to +6 V

IOVCC to GND

−0.3 V to +6 V

V− to GND

−6 V to +0.3 V

VDDx to GND

−0.3 V to (VCC + 0.3 V)

VDDx to V−

−0.3 V to +10 V

OUTx to GND

(V− − 0.3 V) to (VDDx + 0.3 V)

MUX

(V− − 0.3 V) to (VCC + 0.3 V)

REF, REFCOMP, FSADJ

−0.3 V to minimum (VCC + 0.3 V, 6 V)

CS/LD, SCK, SDI, LDAC, CLR,

TGP to GND

−0.3 V to +6 V

FAULT to GND

−0.3 V to +6 V

SDO

–0.3 V to minimum (VCC + 0.3 V, 6 V)

Temperature

Operating Range (TJ)

−40°C to +125°C

Storage Range

−65°C to +150°C

Junction, TJMAX

150°C

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress

rating only; functional operation of the product at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum operat-

ing conditions for extended periods may affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to PCB

thermal design is required.

Thermal characteristics are specified for the worst-case conditions,

that is, a device soldered in a circuit board for surface-mount pack-

ages. Thermal resistance values specified in Table 5 are simulated

based on JEDEC specifications using a 2S2P thermal test board

(see JEDEC JESD51), except for θJC-TOP, which uses a JEDEC 1S

test board.

θJA is the junction to ambient thermal resistance, measured in a

JEDEC natural convection environment.

θJC is the junction to case thermal resistance, measured at the cen-

ter of the package top surface, with an infinite heat sink attached to

the package surface.

θJB is the junction to board thermal resistance, measured at a point

on the board 1 mm from the package edge, along the package

center line, measured in a JEDEC θJB environment.

ΨJB is the junction to board thermal characterization parameter,

measured in a JEDEC natural convection environment.

ΨJT is the junction to package top thermal characterization parame-

ter, measured in a JEDEC natural convection environment.

Do not use θJA, θJC, and θJB thermal resistances to perform direct

calculation/measurement of the die temperature because doing so

results in incorrect values. The thermal resistances assume 100%

of the power that is dissipated along the specified path between the

measurement points. The thermal resistances are directly depend-

ent on the PCB design and environment.

If direct measurement of the package is required, the ΨJT and ΨJB

values must be used because they more accurately reflect the true

thermal dissipation paths.

θJC must only be used where an external heat sink is attached

directly to the package.

System level thermal simulation is highly recommended.

For more details about the thermal resistances, refer to JE-

DEC51-12: Guidelines for Reporting and Using Electronic Package

Thermal Information.

Table 5. Thermal Resistance

Package Type

θJA

θJB

θJC-TOP ΨJT

ΨJB

Unit

05-08-16931

28.34

9.27

17.33

0.11

9.20

°C/W

CB-36-91

29.56

3.85

0.18

0.36

3.62

°C/W

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with no bias. See JEDEC JESD-51.

ELECTROSTATIC DISCHARGE (ESD) RATINGS

The following ESD information is provided for handling of ESD-sen-

sitive devices in an ESD protected area only.

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Field induced charged device model (FICDM) per ANSI/ESDA/JE-

DEC JS-002.

Table 6. LTC2672, 36-Ball WLCSP and 32-lead LFCSP

Package Type ESD Model

Withstand Voltage (V)

Class

36-Ball

WLCSP

HBM

3000

FICDM

1250

32-lead LFCSP HBM

3000

FICDM

2000

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devi-

ces and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

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