LTC2672 datasheet(21/27 Pages) AD

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Data Sheet

LTC2672

THEORY OF OPERATION

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Rev. B | 21 of 27

DAISY-CHAIN OPERATION

The serial output of the shift register appears at the SDO pin. Data

transferred to the device from the SDI input is delayed for 32 SCK

rising edges before being output at the next SCK falling edge so

that the data can be clocked into the microprocessor on the next

32 SCK rising edges.

The SDO output can be used to facilitate control of multiple serial

devices from a single 3-wire serial port (SCK, SDI, and CS/LD).

This kind of daisy-chain series is configured by connecting the SDO

of each upstream device to the SDI of the next device in the chain.

The shift registers of the devices are thus connected in series to

effectively form a single input shift register that extends through

the entire chain. Because of this connection, the devices can be

addressed and controlled individually by concatenating their input

words (the first instruction addresses the last device in the chain,

and so on). The SCK and CS/LD signals are common to all devices

in the series.

When in use, CS/LD is first taken low. Then, the concatenated input

data is transferred to the chain using the SDI of the first device

as the data input. When the data transfer is complete, CS/LD

is taken high, which completes the instruction sequence for all

devices simultaneously. A single device can be controlled by using

the no operation command (1111b) for all other devices in the chain.

When CS/LD is taken high, the SDO pin presents a high impedance

output. Therefore, a pull-up resistor is required at the SDO of each

device (except the last) for daisy-chain operation.

ECHO READBACK

The SDO pin can verify data transfers to the device. During each

32-bit instruction cycle, the SDO pin outputs the previous 32-bit

instruction for verification. The 8-bit don’t care prefix is replaced

by eight fault register status bits, followed by the 4-bit command

and address words and the full 16-bit data word (see Figure 3 ).

The SDO sequence for a 24-bit instruction cycle is the same,

except that the data word is truncated to 8 bits (see Figure 4 ).

When CS/LD is high, SDO presents a high impedance output and

releases the bus for use by other SPI devices.

MONITOR MULTIPLEXER

The LTC2672 includes a multiplexer for monitoring both the voltag-

es and currents at the five current output pins (OUTx). Additionally,

VDDx, V−, VCC, VREF, and the die temperature can all be monitored.

The MUX pin is intended for use with high impedance inputs only.

The impedance at the MUX pin is typically 15 kΩ. The continuous

dc output current at the MUX pin must be limited to ±1 mA to avoid

damaging internal circuitry.

The operating range of the multiplexer extends rail-to-rail from V− to

VCC, and its output is disabled (high impedance) at power-up.

The syntax and codes for the multiplexer command are shown in

Figure 31 and Table 11.

MUX COMMAND

MUX CONTROL CODE

DON’T CARE

Figure 31. Multiplexer Command

Table 11. Analog Multiplexer Control Address Bits

Multiplexer Signal Output

Notes1

Disabled (high-Z)

OUT0 current measurement

IOUT0 = full-scale current (IFS) × VMUX/VREF

OUT1 current measurement

IOUT1 = IFS × VMUX/VREF

OUT2 current measurement

IOUT2 = IFS × VMUX/VREF

OUT3 current measurement

IOUT3 = IFS × VMUX/VREF

OUT4 current measurement

IOUT4 = IFS × VMUX/VREF

VCC

VREF

VREFLO

DAC ground (0 V) reference

Die temperature, T

T = 25°C + (1.4 V − VMUX)/(0.0037 V/°C)

VDD0

VDD1

VDD2

VDD3

VDD4

V–

GND

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