Data Sheet

LTC2672

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. B | 11 of 27

Table 7. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

LFCSP

WLCSP

proportional to the voltage at REF and are inversely proportional to RFSADJ. If FSADJ is tied to VCC, an internal RFSADJ

(20 kΩ) is selected, which results in nominal output ranges. An external resistor of 19 kΩ to 41 kΩ can be used instead

by connecting the resistor between FSADJ and GND. In this case, the external resistor controls the scaling of the ranges,

and the internal resistor is automatically disconnected. See Table 10 for details. When using an external resistor, FSADJ

is sensitive to stray capacitance and must be compensated with a snubber network that consists of a series combination

of 1 kΩ and 1 µF connected in parallel to RFSADJ. With the recommended compensation, FSADJ is stable while driving

stray capacitance up to 50 pF.

13, 27

B3, F3

VCC

Analog Supply Voltage. 2.85 V ≤ VCC ≤ 5.5 V. All output supply voltages must be less than or equal to VCC, (VDDx ≤ VCC).

Bypass VCC to GND with a 1 µF capacitor.

15, 26

A2, F2

V−

Negative Supply Voltage. −5.5 V ≤ V− ≤ GND. Bypass V− to GND with a 1 µF capacitor unless V− is connected to GND.

See Figure 32 for safe operating voltages.

16, 19, 20, 23,

24

F1, D2, D1,

B1, B2

OUT4 to OUT0 DAC Analog Current Outputs. Each current output pin has a dedicated analog supply pin, VDD0 to VDD4. The load

attached to OUTx must be terminated to GND. For information on combining outputs, see the Load Termination and

Combining Channels section.

17, 18, 21, 22,

25

E2, E1, C1,

C2, A1

VDD4 to VDD0

Output Supplies. VDD0 to VDD4 operate at 2.1 V to VCC with respect to GND, and at 2.85 V to 9 V with respect to V−.

These five positive supply inputs provide independent supplies for each of the five DAC current output pins, OUT0 to

OUT4, respectively. Note that the highest output supply voltage must be less than or equal to VCC (VDDx ≤ VCC). Bypass

each supply input to GND separately with a 1 µF capacitor. Unused output supplies must be connected to a valid VCC or

VDDx supply. Do not leave these pins floating. See Figure 32 for safe operating voltages.

28

A3

MUX

Analog Multiplexer Output. Pin voltages and currents can be monitored by measuring the voltage at MUX. When the

multiplexer is disabled, MUX becomes high impedance. The available multiplexer selections are shown in Table 11.

29

B4

IOVCC

Digital Input and Output Supply Voltage. 1.71 V ≤ IOVCC ≤ VCC + 0.3 V. Bypass IOVCC to GND with a 0.1 µF capacitor.

30

B5

FAULT

Active Low Fault Detection Pin. This open-drain, N-channel output pulls low when any valid fault condition is detected.

FAULT is released on the next CS/LD rising edge. A pull-up resistor is required (5 kΩ recommended).

31

A4

CLR

Active Low Asynchronous Clear Input. A logic low at this level triggered input clears the device to the default reset code

and output range, which is zero-scale with the outputs off. The control registers are cleared to zero. Logic levels are

determined by IOVCC.

33

N/A

GND

Ground. Solder this pad directly to the analog ground plane.