LTC2686 datasheet(39/45 Pages) AD

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Data Sheet

LTC2686

THEORY OF OPERATION

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when sourcing or sinking up to 55 mA with supply headroom as low

as 2.0 V.

DC output impedance is equivalent to load regulation, and can be

derived from it by simply calculating a change in units from µV/mA

to Ω. The dc output impedance of the amplifier is typically 0.01 Ω

when driving a load with at least 2.0 V of headroom.

When drawing a load current from either rail, the output voltage

headroom with respect to that rail is limited by the typical channel

resistance of the output devices—20 Ω for the high-side output

device and 10 Ω for the low-side output device. Worst case chan-

nel resistances for the high-side and low-side output devices are

estimated to be 36 Ω and 26 Ω, respectively. For example, when

sourcing 1 mA, the maximum output voltage (below Vx+) is 20 Ω

× 1 mA = 20 mV. See Figure 10 and Figure 11 in the Typical

Performance Characteristics section. The amplifiers are stable,

driving capacitive loads of up to 1 nF. If higher capacitive loads are

needed, the compensation pins can be used to stabilize the DAC

output amplifiers (see the Compensation Pins section).

THERMAL OVERLOAD PROTECTION

The LTC2686 protects itself from damage if the die temperature

exceeds 160°C. Each of the eight DAC channels has an independ-

ent temperature sensor. If a particular channel overheats, it shuts

itself down and triggers a TSF fault. That is, the TSF flag in the

fault register is set (see Table 38), and the open-drain FAULT pin

(Pin 38) pulls low. Moreover, the bit corresponding to the channel

in thermal shutdown is set in both the power-down register (see

Table 37) and the thermal shutdown status register (see Table 42).

These registers can be read using Command 25 and Command

31, respectively. All other channels that did not overheat continue

to operate normally. However, if all 16 channels trigger thermal

shutdown, the entire chip powers down, including reference and

bias circuitry. When triggered, all thermally shut down channels

remain in shutdown mode, even if the temperature has fallen. To

exit thermal shutdown mode, the temperature must first decrease

to below about 150°C on all channels. The user can then power up

the shutdown channels in one of four different ways:

►

Reset the FAULT register (Command 13), and reset the power-

down register (Command 8).

►

Issue a software reset using Command 7.

►

Power cycle the device.

►

Issue a reset on the CLR pin (Pin 21). A CS/LD rising edge

releases the pin regardless of die temperature.

Table 42 shows the structure of the thermal shutdown status regis-

ter, which can be read with Command 31. TSDx represents the

thermal shutdown status of Channel x. Because the total load

current of the device can easily exceed 100 mA, carefully evaluate

the die heating potential of the system design. Grounded loads

as low as 1 kΩ can be used without resulting in excessive heat.

Disable thermal protection by using the SPI Command 7 to set the

TSD_DIS bit in the configuration register.

Table 42. Read Thermal Shutdown Status Register, Command 31

Command

Code

Byte 1

Byte 2

Byte 3

1111 0111

TSD

C/X C/X C/X C/X C/X C/X

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