LTC2686 datasheet(21/45 Pages) AD

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Data Sheet

LTC2686

THEORY OF OPERATION

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Rev. A | 21 of 45

To ensure data integrity, the device also monitors the number of

bits clocked into the chip and issues a fault condition for an invalid

number of clock cycles. See the Fault Detection section for details.

Figure 48 and Figure 49 show timing waveforms of a typical

32‑bit SPI transaction. The CS/LD pin must be low while bits are

clocked in. The following rising edge of CS/LD completes the SPI

transaction and executes the command. Figure 48 shows a typical

32-bit write command sequence with echo readback. For all write

commands, the command word reappears on the SDO pin with a

latency of one command cycle (echo readback). This latency allows

the user to read back the command from the device and verify

the integrity of the data transfer. Figure 49 shows a typical 32-bit

read command sequence. In this example, the user reads the fault

with a latency of one command cycle during the transmission of the

next command word.

Figure 50 shows a typical 24-bit read command sequence. A 24‑bit

read command differs from a 32-bit read command in that only

the requested data appears with a latency of one command cycle

during the transmission of the next command word. The first eight

bits do not show the read command that was executed. Instead,

ignore those bits. Note that echo readback is not available when

24-bit command words are used.

For the detailed structure of command words, refer to the Writing

Codes to DACs section and the Read Commands section.

Figure 48. Typical Write Command Sequence for 32-Bit Words, with Echo Readback

Figure 49. Typical Read Command Sequence for 32-Bit Words, X = Don’t Care

Figure 50. Typical Read Command Sequence for 24-Bit Words

LTC2686 Datasheet(PDF) 21 Page - Analog Devices