LTC2686 datasheet(42/45 Pages) AD

42 / 45 page

Data Sheet

LTC2686

COMMAND ADDRESSES

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Rev. A | 42 of 45

The syntax of the read commands is identical to the corresponding

write commands. For instance, Command 24 (read configuration

ter, Command 7. The bit structure of Command 16 and Command

17 is the same as Command 1. Blank cells in Table 43 mean not

applicable.

Table 43. Write Commands

Command No. Instruction

Command

Address

Bit(s)

Bit Name

Description

Reset

Value

R/W

Write code to DAC

Channel x

0x0 A[3:0]

[23:8]

D15 to D0

16-bit DAC code of Channel A[3:0] for LTC2686-16.

All 0

[23:12]

D11 to D0

12-bit DAC code of Channel A[3:0] for LTC2686-12.

Write channel settings to

DAC Channel x (A[3:0])

0x1 A[3:0]

Mode

Toggle mode register. When the mode bit is set, the

device is in toggle mode. When the mode bit is reset, the

device is in dither mode.

R/W

[18:17]

DIT_PH1,

DIT_PH0

Dither phase, sets the phase of the sinusoidal dither

signal (see Table 35).

R/W

[16:14]

DIT_PER2,

DIT_PER1,

DIT_PER0

Dither Period N, sets the Period N of sinusoidal dither

signal (see Table 34).

000

R/W

[13:12]

TD_SEL1,

TD_SEL0

Controls the toggle select mux that chooses between the

three toggle pins and the software pin (see Table 36).

R/W

[11:8]

S3 to S0

Span settings (see Table 14 and Table 15).

0x0

R/W

Write offset adjust to

DAC Channel x

0x2 A[3:0]

[23:10]

O13 to O0

DAC offset adjust value of Channel A[3:0].

All 0

Write gain adjust to DAC

Channel x

0x3 A[3:0]

[23:8]

G15 to G0

DAC gain adjust value of Channel A[3:0] for LTC2686-16. All 0

[23:12]

G11 to G0

DAC gain adjust value of Channel A[3:0] for LTC2686-12.

Write code to DAC

Channel n, update DAC

Channel x

0x4 A[3:0]

[23:8]

D15 to D0

16-bit DAC code of Channel A[3:0] for LTC2686-16.

All 0

[23:12]

D11 to D0

12-bit DAC code of Channel A[3:0] for LTC2686-12.

Write code to DAC

Channel x, update all

DAC channels

0x5 A[3:0]

[23:8]

D15 to D0

16-bit DAC code of Channel A[3:0] for LTC2686-16.

All 0

[23:12]

D11 to D0

12-bit DAC code of Channel A[3:0] for LTC2686-12.

Update DAC Channel x

0x06 A[3:0]

[5:0]

Updates the DAC register for Channel x.

Write Configuration

0x70

RST

Software reset. Writing a 1 to RST performs a software

reset.

TSD_DIS

Thermal shutdown disable. When TSD_DIS = 1, thermal

shutdown is disabled for all DAC channels.

R/W

EXT_REF

External reference mode. Setting EXT_REF = 1 sets the

external reference mode and disables the REFCOMP

charging current.

R/W

SPI_CRC

SPI cyclic redundancy check. Setting SPI_CRC = 1

enables the CRC.

R/W

Write power-down

0x71

[23:8]

P7 to P0

Power-down register controlling the power-down status of

all DAC channels. P[7:0] controls DAC Channel x. P[7:0]

= 1 powers down the DAC Channel x, P[7:0] = 0 powers

up the DAC Channel x.

All 0

R/W

Write A/B select register

0x72

[23:8]

AB7 to AB0

A/B select register controlling access to DAC Input

ABx controls DAC Channel x. Reset ABx to write to Input

All 0

R/W

Write software toggle bit

0x73

[23:8]

TB7 to TB0

Software toggle bit register acting as a software

controlled toggle bit for each DAC channel. TBx controls

DAC Channel x. When TBx changes from 1 to 0, DAC

Channel x updates to Register A. When TBx changes

from 0 to 1, DAC Channel x updates to Register B.

All 0

R/W

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