LTC2686 datasheet(20/45 Pages) AD

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Data Sheet

LTC2686

THEORY OF OPERATION

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Rev. A | 20 of 45

Figure 47. Block Diagram

The LTC2686 is an 8-channel, ±15 V DAC with selectable output

ranges and an integrated precision reference. The DAC operates

on a positive 5 V VCC supply, and the outputs are driven by bipolar

supply rails (V1+, V2+, and V−). V1+ and V2+ can operate as low

as VCC, and the negative V− supply can operate at ground, making

the devices compatible with single-supply systems. V1+ and V2+

can operate as high as +21 V (V1+ must be greater than or equal

to V2+). V− can operate as low as −21 V, making the LTC2686

robust in industrial environments where high voltage fault protection

is critical.

The output amplifiers offer true rail-to-rail operation and can source

or sink up to 55 mA per DAC channel. The V1+ and V2+ pins can

operate at independent voltages to optimize power efficiency. When

drawing a load current from the V1+, V2+, or V− rails, the output

voltage headroom with respect to that rail is limited by the typical

channel resistance of the output devices.

POWER-ON RESET

The outputs reset when power is first applied, making system

initialization consistent and repeatable. Furthermore, on power-up,

the device resets all internal registers to their default values. The

default output range for all DAC channel outputs is 0 V to 5 V, and

the default DAC code is zero scale.

POWER SUPPLY SEQUENCING

To minimize channel output overshoot and any excess current

during power-up, power up the supplies as follows. If VCC and Vx+

have the same values, tie Vx+ to VCC and power them up first,

and then power up V−. If VCC and Vx+ have different values, power

up Vx+, then VCC, and finally V−. IOVCC does not have a supply se-

quence requirement. For both scenarios, it is recommended to keep

the supply ramp times 10 µs or slower. If an external reference is

used, maintain the voltage at REF within the range of −0.3 V ≤ VREF

≤ VCC + 0.3 V during power-up (see the Absolute Maximum Ratings

section) and tie the REFCOMP pin to ground (see the Reference

Modes section). Take particular care to observe these limits during

power supply turn on and turn off sequences when the voltage at

VCC is in transition. On power-up, immediately perform a software

reset.

Supply bypassing is critical to achieving optimal performance. For

optimal performance, establish at least 1 µF to ground on the VCC,

V+, and V− supplies, and establish at least 0.1 µF of low, 100 mΩ,

effective series resistance (ESR) capacitance for each supply, as

close to the device as possible. The larger capacitor can be omitted

for IOVCC.

SERIAL INTERFACE

When the CS/LD pin is taken low, the data on the SDI pin is

loaded into the shift register on the rising edges of the clock (SCK).

Data can only be transferred to the LTC2686 when the CS/LD

signal is low. The rising edge of CS/LD ends the data transfer

and causes the device to carry out the action specified. For the

LTC2686, the total word length can be 24 bits (3 bytes) or 32 bits

(4 bytes). The leading command/address byte is followed by two

data bytes and an optional third that contains an optional 6-bit cyclic

redundancy check (CRC) code. See the SPI Cyclic Redundant

Check Enable/Disable section for details.

CRC checking is only supported for a word length of 32 bits (4

bytes). In daisy-chain mode, internal register length requires the

clock count to be multiples of 32. See the Daisy-Chain Mode

section for details.

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