LTC2686 datasheet(11/45 Pages) AD

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Data Sheet

LTC2686

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 11 of 45

Table 7. Pin Function Descriptions—WLCSP (Continued)

Pin No.

Mnemonic

Description

REFCOMP

Internal Reference Compensation. For low noise and reference stability, tie REFCOMP to a 0.1 μF capacitor to

GND. Tying REFCOMP to GND causes the device to power up with the internal reference disabled, allowing the

use of an external reference at start up.

A4, B4, G6, H5, H6

REFL

Reference Low Pins. Signal ground for all DAC channels and internal reference. Tie the REFL pins to a clean

analog ground plane.

A5, B5

VCC

Analog Supply Voltage Input. 4.75 V ≤ VCC ≤ 5.25 V. Bypass VCC to GND with a 1 μF capacitor.

A6, C2, C3, C4, C5, C6,

C7, D3, D4, D5, D6, E3, E4,

E5, E6, F3, F4, F5, F6

GND

Analog Ground. Tie GND to a clean analog ground plane.

F2, A7, B7

TGP0, TGP1, TGP2

Asynchronous Toggle and Sinusoidal Dither Multifunctional Pins. In toggle mode, a falling edge updates the DAC

B. In sinusoidal dither mode, the toggle pins function as dither clock inputs. DAC outputs update on the rising

edge. Toggle and dither operations only affect those DAC channels with their toggle/dither enable bit (ENx) set to

1. When neither toggle nor dither operations are used,tie the TGPx pins to GND, and set EN to 0. Logic levels are

determined by IOVCC.

Not Internally Connected.

C8, D7, E7, G8, E2, E1, D2,

COMP0 to COMP7

Compensation Pins for DAC Output Drivers. When driving high capacitive loads, connect a capacitor between

VOUTx and its respective COMPx pin.

B8, D8, E8, F8, G1, F1, D1,

VOUT0 to VOUT7

DAC Analog Voltage Outputs.

REF

Reference Input/Output. The voltage at the REF pin sets the full-scale range of all channels. By default, the internal

reference is routed to this pin. The REF pin must be buffered when driving external dc load currents. When set to

external reference mode, the internal reference is disconnected, and the REF pin becomes a high impedance input

to which a precision external reference can be applied. For low noise and reference stability, tie a capacitor from the

REF pin to GND. The value must be less than the capacitance at the REFCOMP pin. In external reference mode,

the allowable reference input voltage range is 2.0 V to VCC − 0.6 V.

FAULT

Fault Indicator. FAULT is an open-drain, N channel output that pulls low when a fault condition occurs. A fault

condition is detected when the junction temperature exceeds 160°C or when an SPI transaction error occurs. The

FAULT pin is released on the next CS/LD rising edge. A pull-up resistor of ≥10 kΩ is recommended.

MUXOUT

Analog Multiplexer Output. Any of the 16 DAC output pin voltages, current load sense voltages (VSENSE), and

junction temperatures can be monitored by measuring the voltage at the MUX pin. When the mux is disabled, the

MUX pin becomes high impedance. A full listing of available mux functions is given in Table 23.

G7, H8

V1+

Analog Positive Supply for the VOUT0 to VOUT7 DAC Outputs. Bypass V1+ to GND with a 1 μF capacitor. V1+

must be greater than or equal to V2+.

G2, H1

IOVCC

Digital Input/Output Supply Voltage. 1.71 V ≤ IOVCC ≤ VCC + 0.3 V. Bypass IOVCC to GND with a 0.1 μF

capacitor.

SDI

Serial Interface Data Input. Data on SDI is clocked into the DAC on the rising edge of SCK. The LTC2686 accepts

input word lengths of 24 bits or 32 bits. Logic levels are determined by IOVCC.

SCK

Serial Interface Clock Input. Logic levels are determined by IOVCC.

SDO

Serial Interface Data Output. Data is clocked out onto SDO by the falling edge of SCK. SDO is high impedance

when CS/LD is high. Logic levels are determined by IOVCC.

LDAC

Active Low Asynchronous DAC Update Pin. When CS/LD is high, a falling edge on LDAC updates all DAC registers

with the contents of the input registers. When LDAC is low, a rising edge on CS/LD similarly updates all DAC

registers. Logic levels are determined by IOVCC. If the LDAC pin is not used, tie it high to IOVCC. Updates can

then be performed through SPI commands.

CLR

Active Low Asynchronous Clear Input. A logic low at this level triggered input clears the device to zero-scale code

and a 0 V to 5 V span range. The control registers are cleared to default values. Logic levels are determined by

IOVCC.

CS/LD

Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the

executed. Logic levels are determined by IOVCC.

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