LLCC68 datasheet(45/106 Pages) SEMTECH

45 / 106 page

LLCC68

Data Sheet

Rev. 1.0

DS.LLCC68.W.APP

July 2019

45 of 106

Semtech

www.semtech.com

8. Digital Interface and Control

The LLCC68 is controlled via a serial SPI interface and a set of general purpose input/output (DIOs). At least one DIO must

be used for IRQ and the BUSY line is mandatory to ensure the host controller is ready to accept the commands. The LLCC68

uses an internal controller (CPU) to handle communication and chip control (mode switching, API etc...). BUSY is used as a

busy signal indicating that the chip is ready for new command only if this signal is low. When BUSY is high, the host

controller must wait until it goes down again before sending another command. Through SPI the application sends

commands to the internal chip or access directly the data memory space.

8.1 Reset

A complete “factory reset” of the chip can be issued on request by toggling pin 15 NRESET of the LLCC68. It will be

automatically followed by the standard calibration procedure and any previous context will be lost. The pin should be held

low for typically 100 μs for the Reset to happen.

8.2 SPI Interface

The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL

= 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented.

An address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received

for the read access. The NSS pin goes low at the beginning of the frame and goes high after the data byte.

MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising

edge of SCK. MISO is generated by the slave on the falling edge of SCK.

A transfer is always started by the NSS pin going low. MISO is high impedance when NSS is high.

The SPI runs on the external SCK clock to allow high speed up to 16 MHz.

8.2.1 SPI Timing When the Transceiver is in Active Mode

In this mode the chip is able to handle SPI command in a standard way i.e. no extra delay needed at the first SPI transaction.

Figure 8-1: SPI Timing Diagram

LLCC68 Datasheet(PDF) 45 Page - Semtech Corporation