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AM3359 Datasheet(PDF) 124 Page - Texas Instruments |
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AM3359 Datasheet(HTML) 124 Page - Texas Instruments |
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124 / 256 page  RGMII[x]_RD[3:0] (B) RGMII[x]_RCTL (B) RGMII[x]_RCLK (A) 1 RXERR 1st Half-byte 2nd Half-byte 2 RXDV RGRXD[3:0] RGRXD[7:4] RGMII[x]_RCLK 2 3 1 124 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 SPRS717L – OCTOBER 2011 – REVISED MARCH 2020 www.ti.com Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright © 2011–2020, Texas Instruments Incorporated 7.6.1.4 EMAC and Switch RGMII Electrical Data and Timing Table 7-18. Timing Requirements for RGMII[x]_RCLK - RGMII Mode (see Figure 7-13) NO. 10 Mbps 100 Mbps 1000 Mbps UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 1 tc(RXC) Cycle time, RXC 360 440 36 44 7.2 8.8 ns 2 tw(RXCH) Pulse duration, RXC high 160 240 16 24 3.6 4.4 ns 3 tw(RXCL) Pulse duration, RXC low 160 240 16 24 3.6 4.4 ns 4 tt(RXC) Transition time, RXC 0.75 0.75 0.75 ns Figure 7-13. RGMII[x]_RCLK Timing - RGMII Mode Table 7-19. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode (see Figure 7-14) NO. 10 Mbps 100 Mbps 1000 Mbps UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 1 tsu(RD-RXC) Setup time, RD[3:0] valid before RXC high or low 1 1 1 ns tsu(RX_CTL-RXC) Setup time, RX_CTL valid before RXC high or low 1 1 1 2 th(RXC-RD) Hold time, RD[3:0] valid after RXC high or low 1 1 1 ns th(RXC-RX_CTL) Hold time, RX_CTL valid after RXC high or low 1 1 1 3 tt(RD) Transition time, RD 0.75 0.75 0.75 ns tt(RX_CTL) Transition time, RX_CTL 0.75 0.75 0.75 A. RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the respective timing requirements. B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL carries RXDV on rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK. Figure 7-14. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode |
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