AM3359 datasheet(127/256 Pages) TI1

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

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SPRS717L – OCTOBER 2011 – REVISED MARCH 2020

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Peripheral Information and Timings

Table 7-24. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

1 / tc(clk)

Frequency(18), output clock gpmc_clk

100

MHz

tw(clkH)

Typical pulse duration, output clock gpmc_clk high

0.5P(15)

tw(clkL)

Typical pulse duration, output clock gpmc_clk low

0.5P(15)

tdc(clk)

Duty cycle error, output clock gpmc_clk

–500

500

–500

500

tJ(clk)

Jitter standard deviation(19), output clock gpmc_clk

33.33

td(clkH-csnV)

Delay time, output clock gpmc_clk rising edge to

output chip select gpmc_csn[x](14) transition

F(6) - 2.2

F(6) + 4.5

F(6) - 3.2

F(6) + 9.5

td(clkH-csnIV)

Delay time, output clock gpmc_clk rising edge to

output chip select gpmc_csn[x](14) invalid

E(5) – 2.2

E(5) + 4.5

E(5) – 3.2

E(5) + 9.5

td(aV-clk)

Delay time, output address gpmc_a[27:1] valid to

output clock gpmc_clk first edge

B(2) – 4.5

B(2) + 2.3

B(2) – 5.5

B(2) + 12.3

td(clkH-aIV)

Delay time, output clock gpmc_clk rising edge to

output address gpmc_a[27:1] invalid

–2.3

4.5

–3.3

14.5

td(be[x]nV-clk)

Delay time, output lower byte enable and command

latch enable gpmc_be0n_cle, output upper byte

enable gpmc_be1n valid to output clock gpmc_clk

first edge

B(2) – 1.9

B(2) + 2.3

B(2) – 2.9

B(2) + 12.3

td(clkH-be[x]nIV)

Delay time, output clock gpmc_clk rising edge to

output lower byte enable and command latch enable

gpmc_be0n_cle, output upper byte enable

gpmc_be1n invalid(11)

D(4) – 2.3

D(4) + 1.9

D(4) – 3.3

D(4) + 6.9

td(clkL-be[x]nIV)

Delay time, gpmc_clk falling edge to

gpmc_nbe0_cle, gpmc_nbe1 invalid(12)

D(4) – 2.3

D(4) + 1.9

D(4) – 3.3

D(4) + 6.9

td(clkL-be[x]nIV)

Delay time, gpmc_clk falling edge to

gpmc_nbe0_cle, gpmc_nbe1 invalid(13)

D(4) – 2.3

D(4) + 1.9

D(4) – 3.3

D(4) + 11.9

td(clkH-advn)

Delay time, output clock gpmc_clk rising edge to

output address valid and address latch enable

gpmc_advn_ale transition

G(7) – 2.3

G(7) + 4.5

G(7) – 3.3

G(7) + 9.5

td(clkH-advnIV)

Delay time, output clock gpmc_clk rising edge to

output address valid and address latch enable

gpmc_advn_ale invalid

D(4) – 2.3

D(4) + 3.5

D(4) – 3.3

D(4) + 9.5

F10

td(clkH-oen)

Delay time, output clock gpmc_clk rising edge to

output enable gpmc_oen transition

H(8) – 2.3

H(8) + 3.5

H(8) – 3.3

H(8) + 8.5

F11

td(clkH-oenIV)

Delay time, output clock gpmc_clk rising edge to

output enable gpmc_oen invalid

H(8) – 2.3

H(8) + 3.5

H(8) – 3.3

H(8) + 8.5

F14

td(clkH-wen)

Delay time, output clock gpmc_clk rising edge to

output write enable gpmc_wen transition

I(9) – 2.3

I(9) + 4.5

I(9) – 3.3

I(9) + 9.5

F15

td(clkH-do)

Delay time, output clock gpmc_clk rising edge to

output data gpmc_ad[15:0] transition(11)

J(10) – 2.3

J(10) + 1.9

J(10) – 3.3

J(10) + 6.9

F15

td(clkL-do)

Delay time, gpmc_clk falling edge to gpmc_ad[15:0]

data bus transition(12)

J(10) – 2.3

J(10) + 1.9

J(10) – 3.3

J(10) + 6.9

F15

td(clkL-do)

Delay time, gpmc_clk falling edge to gpmc_ad[15:0]

data bus transition(13)

J(10) – 2.3

J(10) + 1.9

J(10) – 3.3

J(10) + 11.9

F17

td(clkH-be[x]n)

Delay time, output clock gpmc_clk rising edge to

output lower byte enable and command latch enable

gpmc_be0n_cle transition(11)

J(10) – 2.3

J(10) + 1.9

J(10) – 3.3

J(10) + 6.9

F17

td(clkL-be[x]n)

Delay time, gpmc_clk falling edge to

gpmc_nbe0_cle, gpmc_nbe1 transition(12)

J(10) – 2.3

J(10) + 1.9

J(10) – 3.3

J(10) + 6.9

F17

td(clkL-be[x]n)

Delay time, gpmc_clk falling edge to

gpmc_nbe0_cle, gpmc_nbe1 transition(13)

J(10) – 2.3

J(10) + 1.9

J(10) – 3.3

J(10) + 11.9

F18

tw(csnV)

Pulse duration, output chip select

gpmc_csn[x](14) low

Read

A(1)

Write

A(1)

F19

tw(be[x]nV)

Pulse duration, output lower byte enable

and command latch enable

gpmc_be0n_cle, output upper byte enable

gpmc_be1n low

Read

C(3)

Write

C(3)

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