AM3359 datasheet(129/256 Pages) TI1

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

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SPRS717L – OCTOBER 2011 – REVISED MARCH 2020

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Peripheral Information and Timings

(8) For OE falling edge (OE activated) and I/O DIR rising edge (Data Bus input direction):

–

Case GpmcFCLKDivider = 0:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK(17)

–

Case GpmcFCLKDivider = 1:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and

OEOnTime are even)

–

H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime) is a multiple of 3)

–

H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)

–

H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)

For OE rising edge (OE deactivated):

–

Case GpmcFCLKDivider = 0:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK(17)

–

Case GpmcFCLKDivider = 1:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and

OEOffTime are even)

–

H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime) is a multiple of 3)

–

H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)

–

H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)

(9) For WE falling edge (WE activated):

–

Case GpmcFCLKDivider = 0:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK(17)

–

Case GpmcFCLKDivider = 1:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and

WEOnTime are even)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime) is a multiple of 3)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)

–

I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)

For WE rising edge (WE deactivated):

–

Case GpmcFCLKDivider = 0:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK (17)

–

Case GpmcFCLKDivider = 1:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and

WEOffTime are even)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime) is a multiple of 3)

–

I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)

–

I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)

(10) J = GPMC_FCLK(17)

(11) First transfer only for CLK DIV 1 mode.

(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.

(13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.

(14) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.

(15) P = gpmc_clk period in ns

(16) For read: K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(18) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the

GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.

(19) The jitter probability density can be approximated by a Gaussian function.

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