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H838024R Datasheet(PDF) 144 Page - Renesas Technology Corp |
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H838024R Datasheet(HTML) 144 Page - Renesas Technology Corp |
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144 / 697 page  Section 3 Exception Handling Rev. 7.00 Mar 10, 2005 page 102 of 652 REJ09B0042-0700 • Example of a malfunction When flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1 (bit 1 of IRR1). MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time AND.B #B'11111101,R1L ..... Here, IRRI0 = 1 MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0 In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B instruction is executing. The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1, IRRI0 is also cleared. |
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