PM4328 datasheet(39/250 Pages) PMC

39 / 250 page

STANDARD PRODUCT

PM4328 TECT3

DATASHEET

PMC-2011596

ISSUE 1

HIGH DENSITY T1/E1 FRAMER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

PIN DESCRIPTION

Pin Name

Type

No.

Function

DS3 Line Side Interface

RCLK

Input

W5 Receive Input Clock (RCLK). RCLK provides the

receive direction timing. RCLK is a DS3, nominally a

44.736 MHz, 50% duty cycle clock input.

RPOS/RDAT

Input

Positive Input Pulse (RPOS). RPOS represents the

positive pulses received on the B3ZS-encoded DS3

when dual rail input format is selected.

Receive Data Input (RDAT). RDAT represents the

NRZ (unipolar) DS3 input data stream when single rail

input format is selected.

RPOS and RDAT are sampled on the rising edge of

RCLK by default and may be enabled to be sampled

on the falling edge of RCLK by setting the RFALL bit in

the DS3 Master Receive Line Options register.

RNEG/RLCV

Input

AB6 Negative Input Pulse (RNEG). RNEG represents the

negative pulses received on the B3ZS-encoded DS3

when dual rail input format is selected.

Line code violation (RLCV). RLCV represents receive

line code violations when single rail input format is

selected.

RNEG and RLCV are sampled on the rising edge of

RCLK by default and may be enabled to be sampled

on the falling edge of RCLK by setting the RFALL bit in

the DS3 Master Receive Line Options register.

TCLK

Output AA7 Transmit Clock (TCLK). TCLK provides timing for

circuitry downstream of the DS3 transmitter of the

TECT3. TCLK is nominally a 44.736 MHz, 50% duty

cycle clock.

PM4328 Datasheet(PDF) 39 Page - PMC-Sierra, Inc

PM4328 Datasheet(HTML) 39 Page - PMC-Sierra, Inc

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