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PM4328 Datasheet(PDF) 16 Page - PMC-Sierra, Inc

Part # PM4328
Description  HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER
PDF  250 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM4328 Datasheet(HTML) 16 Page - PMC-Sierra, Inc

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STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
3
· Provides Red, Yellow, and AIS alarm integration.
· Provides ESF bit-oriented code detection and an HDLC/LAPD interface for
terminating the ESF facility data link.
· Indicates signaling state change, and two superframes of signaling debounce
on a per-DS0 basis.
· Provides an HDLC interface with 128 bytes of buffering for terminating the
facility data link.
· Provides performance monitoring counters sufficiently large as to allow
performance monitor counter polling at a minimum rate of once per second.
Optionally, updates the performance monitoring counters and interrupts the
microprocessor once per second, timed to the receive line.
· Provides an optional elastic store which may be used to time the ingress
streams to a common clock and frame alignment, or to facilitate per-DS0
loopbacks.
· Provides DS-1 robbed bit signaling extraction, with optional data inversion,
programmable idle code substitution, digital milliwatt code substitution, bit
fixing, and two superframes of signaling debounce on a per-channel basis.
· A pseudo-random sequence user selectable from 2
11 –1, 215 –1 or220 –1, may
be detected in the T1 stream in either the ingress or egress directions. The
detector counts pattern errors using a 24-bit non-saturating PRBS error
counter. The pseudo-random sequence can be the entire T1 or any
combination of DS0s within a framed T1.
· Line side interface is the DS3 interface via the M13 multiplex.
· System side interface is either serial clock and data, H-MVIP or SBI bus.
· Frames in the presence of and detects the “Japanese Yellow” alarm.
· Provides external access for up to two de-jittered recovered T1 clocks.
Each one of 21 E1 receiver sections:
· Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals.
The framing procedures are consistent ITU-T G.706 specifications.
· Provides an HDLC interface with 128 bytes of buffering for terminating the
national use bit data link.



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