PM4328 datasheet(45/250 Pages) PMC

45 / 250 page

STANDARD PRODUCT

PM4328 TECT3

DATASHEET

PMC-2011596

ISSUE 1

HIGH DENSITY T1/E1 FRAMER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

T1 and E1 System Side Serial Clock and Data Interface

ICLK[1]/ISIG[1]

ICLK[2]/ISIG[2]

ICLK[3]/ISIG[3]

ICLK[4]/ISIG[4]

ICLK[5]/ISIG[5]

ICLK[6]/ISIG[6]

ICLK[7]/ISIG[7]

ICLK[8]/ISIG[8]

ICLK[9]/ISIG[9]

ICLK[10]/ISIG[10]

ICLK[11]/ISIG[11]

ICLK[12]/ISIG[12]

ICLK[13]/ISIG[13]

ICLK[14]/ISIG[14]

ICLK[15]/ISIG[15]

ICLK[16]/ISIG[16]

ICLK[17]/ISIG[17]

ICLK[18]/ISIG[18]

ICLK[19]/ISIG[19]

ICLK[20]/ISIG[20]

ICLK[21]/ISIG[21]

ICLK[22]/ISIG[22]

ICLK[23]/ISIG[23]

ICLK[24]/ISIG[24]

ICLK[25]/ISIG[25]

ICLK[26]/ISIG[26]

ICLK[27]/ISIG[27]

ICLK[28]/ISIG[28]

Output Y3

AB2

AB20

AB21

W22

Y20

H22

F19

AA1

L22

K19

F22

G20

H19

G19

E19

F21

Ingress Clocks (ICLK[1:28]). The Ingress Clocks are

active when the external signaling interface is disabled.

Each ingress clock is optionally a smoothed (jitter

attenuated) version of the associated receive clock

from the DS3 multiplexer. When the Clock Master:

NxChannel mode is active, ICLK[x] is a gapped version

of the smoothed receive clock. When Clock Master:

Full T1/E1 mode is active, IFP[x] and ID[x] are updated

on the active edge of ICLK[x]. When the Clock Master:

NxDS0 mode is active, ID[x] is updated on the active

edge of ICLK[x].

Ingress Signaling (ISIG[1:28]). When the Clock

Slave: External Signaling mode is enabled, each

ISIG[x] contains the extracted signaling bits for each

channel in the frame, repeated for the entire

superframe. Each channel’s signaling bits are valid in

bit locations 5,6,7,8 of the channel and are channel-

aligned with the ID[x] data stream. ISIG[x] is updated

on the active edge of the common ingress clock,

CICLK.

In E1 mode only ICLK[1:21] and ISIG[1:21] are used.

ICLK[1]/ISIG[1] shares a pin with the DS3 system

interface signal RGAPCLK/RSCLK.

IFP[1]

IFP[2]

IFP[3]

IFP[4]

IFP[5]

IFP[6]

IFP[7]

IFP[8]

IFP[9]

IFP[10]

IFP[11]

Output AB5

W20

AA22

Y21

W21

K22

K21

Ingress Frame Pulse (IFP[1:28]). The IFP[x] outputs

are intended as timing references.

IFP[x] indicates the frame alignment or the superframe

alignment of the ingress stream, ID[x].

When Clock Master: Full T1/E1 mode is active, IFP[x]

is updated on the active edge of the associated

ICLK[x]. When Clock Master: NxDS0 mode is active,

ICLK[x] is gapped during the pulse on IFP[x]. When

the Clock Slave ingress modes are active, IFP[x] is

updated on the active edge of CICLK. I the Clear

PM4328 Datasheet(PDF) 45 Page - PMC-Sierra, Inc

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