PM7344 datasheet(259/293 Pages) PMC

259 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

243

The boundary scan architecture consists of a TAP controller, an instruction

and a boundary scan register. The TAP controller interprets the TMS input and

generates control signals to load the instruction and data registers. The

instruction register with instruction decode block is used to select the test to be

executed and/or the register to be accessed. The bypass register offers a single-

bit delay from primary input, TDI to primary output, TDO. The device

identification register contains the device identification code.

The boundary scan register allows testing of board inter-connectivity. The

boundary scan register consists of a shift register place in series with device

inputs and outputs. Using the boundary scan register, all inputs can be sampled

and shifted out on primary output, TDO. In addition, patterns can be shifted in

on primary input, TDI and forced onto all outputs.

TAP Controller

The TAP controller is a synchronous finite state machine clocked by the rising

edge of primary input, TCK. All state transitions are controlled using primary

input, TMS. A description of the finite state machine follows:

PM7344 Datasheet(PDF) 259 Page - PMC-Sierra, Inc