PM7344 datasheet(256/293 Pages) PMC

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PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

240

14.1

Using the JT2F

Figure 31

- J2 Framer Example

JT2F

RCK

TCK

RSD

RSC

RTS

RCG

TTS

TCG

TCOUT

TFOUT

XSD

XCK

XSF

TCIN

SER

6.312 MHz

TCLKI

TDD[x]

TOHI

PM7344

S/UNI-MPH

RDD[x]

RCLKI[x]

ROH[x]

TCLKO[x]

TOHO[x]

The JT2F J2 framer can be connected to the S/UNI-MPH as shown above. The

S/UNI-MPH is configured to select the J2 interface by setting the register bits

MODE[1] to logic 1 and MODE[0] to logic 0. The register bits TFALL, TOHINV,

TRISE, and TDNINV are all set to logic 1 so that TOHI is sampled on the falling

TCLKI edge, TOHI is active low, TDD[x] and TOHO[x] are updated on the rising

edge of TCLKO[x], and TOHO[x] is active low. The register bits RDNINV and

RFALL are set to logic 1 so that ROH[x] is active low and so RDD[x] and ROH[x]

are sampled on the falling edge of RCLKI[x].

Using the ROH and TOHI inputs from the JT2F, the S/UNI-MPH internally

generates additional J2 overhead signals which identify the J2 signalling and

framing bit positions. The S/UNI-MPH also generates the J2 multiframe output

on TOHO. Additional information on the J2 Transmit and Receive timing is

provided in the S/UNI-MPH Functional Timing section.

14.2

Using the Digital Jitter Attenuator

The key to using DJAT lies in selecting the appropriate divisors for the phase

comparison between the selected reference clock and the generated smooth

TCLKO[x].

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