PM7344 datasheet(105/293 Pages) PMC

105 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

LINELB:

The LINELB bit selects the line loopback mode, where the data input on

RDP/RDD[x] and RDN/RLCV/ROH[x] is connected to TDP/TDD[x] and

TDN/TOHO[x] respectively. When LINELB is set to logic 1, the line loopback

mode is enabled. When LINELB is set to logic 0, the line loopback mode is

disabled. When either the J2 or arbitrary framing modes are selected, DJAT

is disabled, and LINELB will reroute the RDD[x], ROH[x], and RCLKI[x]

directly to TDD[x], TOHO[x], and TCLKO[x] respectively. For the J2 framing

format, if the TOHO[x] output is desired to be the multi-frame pulse, PAYLB

should be used instead of LINELB.

DIALB:

The DIALB bit selects the diagnostic loopback mode, where the transmit data

stream is connected to the receive datastream. When DIALB is set to logic

1, the diagnostic digital loopback mode is enabled. When DIALB is set to

logic 0, the diagnostic loopback mode is disabled.

TPERRE:

The TPERRE bit is an interrupt enable. When TPERRE is logic 1, a parity

error detected on the transmit FIFO interface causes a microprocessor

interrupt to be generated. When TPERRE is logic 0, a parity error does not

cause an interrupt.

TPERRI:

When the TPERRI bit is logic 1, it indicates that a parity error was detected

on the incoming transmit FIFO interface. When TPERRI is logic 0, no parity

error was detected. Reading this register clears this bit to logic 0.

PM7344 Datasheet(PDF) 105 Page - PMC-Sierra, Inc