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PM7350-PI Datasheet(PDF) 35 Page - PMC-Sierra, Inc |
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PM7350-PI Datasheet(HTML) 35 Page - PMC-Sierra, Inc |
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35 / 241 page ![]() RELEASED PM7350 S/UNI-DUPLEX DATA SHEET PMC-1980581 ISSUE 5 DUAL SERIAL LINK PHY MULTIPLEXER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23 Ball Name Type Ball No. Function High Speed LVDS Links ICA I/O A3 The Input Cell Available (ICA) signal provides cell- level flow control. ICA’s direction depends on the state of the IMASTER input. As a SCI-PHY/Utopia bus master (IMASTER = 1, IANYPHY = 0) the S/UNI-DUPLEX polls up to 32 PHYs using the PHY address signals IADDR[4:0]. A PHY device being addressed by IADDR[4:0] is expected to indicate whether or not it has a complete cell available for transfer by driving ICA during the clock cycle following that in which it is addressed. When a cell transfer is in progress, the S/UNI-DUPLEX will not poll the PHY device which is sending the cell so PHY devices need not support the cell availability indication during cell transfer. The selection of a particular PHY device from which to transfer a cell is indicated by the state of IADDR[4:0] during the last cycle IENB is high. As a bus slave (IMASTER = 0) the S/UNI-DUPLEX indicates the ability to accept additional cells via the ICA output. When IAVALID is sampled high in SCI- PHY or low in Any-PHY configuration, ICA is asserted if the cell FIFO for the logical channel addressed by IADDR[4:0] has at least one empty cell buffer. If the FIFO is full, ICA is deasserted. If a cell transfer is in progress that will fill a logical channel FIFO, ICA will also be deasserted. When IAVALID is sampled low in SCI-PHY or high in Any- PHY configuration, ICA becomes high impedance. ICA is delayed by an additional clock cycle in Any- PHY configuration. The buffer status for the particular logical channel involved is stale for a maximum of 16 cycles after the start of the cell transfer when using a 8 bit bus or 12 cycles when using a 16 bit bus. Therefore, the master should refrain from polling that logical channel in the interim. |
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