PM7350-PI datasheet(87/241 Pages) PMC

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PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

DUPLEX sees that all far-end channels are congested it will immediately start

sending stuff cells on the upstream serial link (unless it has control channel cells

to send and that channel is not marked as congested). With the worst case

alignment between upstream and downstream links, the S/UNI-DUPLEX may

transmit up to two cells after the cell available deassertion was first registered by

the far-end S/UNI-VORTEX. The FIFO threshold on the S/UNI-VORTEX

accounts for this latency, buffer overflow cannot occur.

Once the far-end S/UNI-VORTEX has a chance to clear cells from its receiver

buffer it will reassert the cell available bit on all channels. Refer to the S/UNI-

VORTEX Data Sheet for further information.

Case #2: the far-end device is a S/UNI-DUPLEX

Unlike the S/UNI-VORTEX, the far-end’s S/UNI-DUPLEX’s LVDS receive buffer

is divided into 32 FIFOS, so it always individually indicates the status of the 32

user channels. This also applies to the control channel – its status in

independent of the status of the user channels.

When the near-end S/UNI-DUPLEX sees that a PHY or control channel is

congested it will take that channel out of the round robin scheduling used to

transfer cells from the buffers to the transmit LVDS link. If none of the remaining

channels have cells to send, or if all channels are experiencing congestion, then

the S/UNI-DUPLEX will automatically broadcast a stuff cell on the two upstream

serial links.

With worst case alignment between upstream and downstream links, the S/UNI-

DUPLEX may transmit up to two cells to a channel after the cell available

deassertion for that channel was first registered by the far-end S/UNI-DUPLEX.

Since the FIFO threshold on the S/UNI-DUPLEX accounts for this latency, buffer

overflow cannot occur on the active link.

Once the far-end S/UNI-DUPLEX has a chance to clear cells from the congested

receive buffer it will reassert the cell available bit on the affected channel.

9.5 Timing Reference Insertion and Recovery

The high-speed serial links are capable of transporting a timing reference

independent of the bit rate. The timing signal received on the active RXD1+/- or

RXD2+/- inputs is presented on RX8K. Rising edges of TX8K input are encoded

in the TXD1+/- and TXD2+/- cells.

Although the timing reference is targeted at a typical need of transporting an 8

kHz signal, its frequency is not constrained to 8 kHz. Any frequency less than

the cell rate is permissible.

PM7350-PI Datasheet(PDF) 87 Page - PMC-Sierra, Inc

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