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PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

9.3.4 Protection Switching Protocol

The S/UNI-DUPLEX and its sister device, the S/UNI-VORTEX inherently support

system architectures requiring fault tolerance and 1:1 redundancy of the

system’s common equipment. In point-to-point backplane architectures such as

these, the 1:1 protection also includes the associated LVDS links connecting the

common equipment to the line cards. The S/UNI-VORTEX and S/UNI-DUPLEX

perform clock recovery, cell delineation, and header error monitoring for all

receive high-speed serial links simultaneously. The maintained error counts and

alarm status indications may be used by the control system to determine the

state and viability of each LVDS link. See the S/UNI-VORTEX data sheet for

additional details.

In these architectures, each S/UNI-DUPLEX will be connected to two S/UNI-

VORTEXs (see Fig. 1) or to two S/UNI-DUPLEXs (see Fig. 5). Upon a failure of

the active card, the spare card becomes the conduit for traffic. The S/UNI-

VORTEX and S/UNI-DUPLEX facilitate link selection upon start-up as well as

switching between links upon failure conditions.

Typically a centralized resource or cooperating distributed microprocessor

subsystems will determine which common card is to be considered active for

each downstream S/UNI-DUPLEX and sets the active indication accordingly.

The current state of the link’s active bit is sent downstream once per transmitted

cell. The active status is debounced and acted upon by the far-end S/UNI-

DUPLEX.

The S/UNI-DUPLEX will only accept data traffic from one of its two LVDS links,

and normally it is the link marked active that is considered the working link

(although this can be overridden locally as discussed below). Thus, although the

far-end S/UNI-VORTEX or S/UNI-DUPLEX may indicate the desired active and

spare links, it is actually the local S/UNI-DUPLEX that must enforce the

protection switching. The link switching mechanism preserves cell integrity on

the high-speed serial link that becomes active. In other words, switching occurs

between cells.

At reset Link 1 is marked as the active link. It is also important to note that a

Loss of Signal (LOS) on the active LVDS link does not automatically affect the

value of the ACTIVE bit. The ACTIVE bit value prior to the LOS condition is

maintained unless the other link’s active indication is asserted (after debouncing)

or until a local override (described below) or device reset is invoked. The value of

the extracted ACTIVE bit is forced to logic 0 when the corresponding link is in

Loss of Cell Delineation (LCD ) state.

If the S/UNI-DUPLEX is auto-selecting its active link status (Master Configuration

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