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VR5510 Datasheet(PDF) 2 Page - NXP Semiconductors |
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VR5510 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 200 page ![]() NXP Semiconductors VR5510 Multi-output PMIC with SMPS and LDO 2 Simplified application diagram aaa-039353 VBAT VR5510 BUCK1 BUCK2 BUCK3 LDO2 LDO1 I2C AMUX CLK Mgt (FSYNC) VPRE MCU WAKE PWRON1 PWRON2 Analog and digital monitoring BOOST FAIL SAFE STATE MACHINE VDD_CORE PCie VDD_DDR_IO VDD_3P3 LDO3 1P8_DDR HVLDO BUCK1 VDD_CORE_STBY VDD_3P3_LP To CAN PHY PGOOD, RSTB INTB STBY_PGOOD FIN FS0B FCCU1/2 STBY Figure 1. VR5510 simplified application diagram 3 Features and benefits • 60 VDC maximum input voltage • VPRE synchronous buck controller with external MOSFETs; configurable output voltage, switching frequency, and current capability up to 10 A • Low-voltage integrated synchronous BUCK1 and BUCK2 converters dedicated to MCU core supply with SVS/ DVS capability; configurable output voltage and current capability up to 3.6 A peak; dual-phase operation to extend the current capability up to 7.2 A peak • Low-voltage integrated synchronous BUCK3 converter; configurable output voltage and current capability up to 3.6 A peak • BOOST converter with integrated low-side switch; configurable output voltage and input current capability up to 2.25 A peak • 3x linear voltage regulators (LDOx) for MCU IOs, double-data rate (DDR) and analog-to-digital converter (ADC) supplies; configurable output voltage and current capability up to 400 mA • High-voltage linear regulator (HVLDO) with current capability up to 10 mA in low dropout (LDO) mode and 100 mA in Switch mode • EMC optimization techniques, including switch-mode power supply (SMPS) frequency synchronization, spread spectrum, slew rate control, manual frequency tuning VR5510 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 2 October 2024 Document feedback 2 / 200 |
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