VR5510 datasheet(13/200 Pages) NXP

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NXP Semiconductors

VR5510

Multi-output PMIC with SMPS and LDO

8.6 Functional state diagram

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From any

FS_state

From any

Main_state

From any

FS_state after

`8s TIMER'

From any FS_state

after `ABIST1'

exclude `PGOOD'

PORB_FS=0 or

FS_ENABLE=0

PORB_FS=1 and

VBOS > VBOS_por

PGOOD=RSTB=FS0B=0

Release PGOOD and RSTB,

FS0B=0

open window based on

WD_INIT_TIMEOUT_OTP[1:0]

PGOOD=RSTB=1, FS0B=0

RSTB=FS0B=0,

PGOOD=0

All disabled

regulators are

powering down at

the same time

RSTB=FS0B=0,

PGOOD=1

PGOOD=RSTB=FS0B=0

FS_READY=1

PGOOD=RSTB=FS0B=0

Start 8s Timer if VDDOTP=0

PGOOD=RSTB=FS0B=0

Unpowered

OFF Mode

Wait 10 µs

FS_ENABLE=0

RSTB_DUR

GOTO_INITFS

(I2C)

LBIST

(OTP)

LBIST done and VDDOTP=0

READY

FS_ENABLE=1 (from Main)

8s TIMER

(Vxx_uv=0 and Vxx_ov=0)

or !Vxx_ABIST1_OTP

ABIST1

DEEP-FS

ABIST1 done

RELEASE

RESET

PGOOD=RSTB=1

INIT_FS

WD_OK

WAIT

ABIST2

WDI asserted and

FCCU_OR_WID_OTP=1

ABIST2

(I2C)

ABIST1_OK and ABIST2_OK

(Vxx_uv=0 and Vxx_ov=0)

or !Vxx_ABIST2_I2C

FS STBY MODE

FS_ENABLE=0

To Unpowered

FS0B

lock

DEEP-FS

VALID_STBY =

(STBY_SAFE_DIS_OTP=1 and STBY pin

transition and ABIST1_ok) or

(STBY_SAFE_DIS_OTP=0 and I2C req and

ABIST_ok and STBY pin transition (before

TIMING_WINDOW_STBY timer

expiration))

ASSERT

RSTB

FLT_ERR_CNT=0

and VDDOTP=0 and

RELEASE_FS0B (I2C)

WD windowing

PGOOD=RSTB=1, FS0B=1

WD windowing

PGOOD=RSTB=1, FS0B=0

FCCU monitoring is enabled

after the first good WD

FS0B_REQ

Valid_STBY

Activate

RSTB

From any FS_state

after `ABIST1'

include `RSTB'

ASSERT

PGOOD

Activate

PGOOD

Standby entry

(coming from FS)

NORMAL_

PORB_MAIN=0 or VBOS

< VBOS_por or VSUP

POR or VPRE_POR

PORB_MAIN=1 and

VBOS > VBOS_por

Note: DS_LOGIC = Deep

Sleep Mode config

Note: Those conditions

will not apply if PSYNC/

PWRON2, OTP disabled

and VSUP > VSUP_UV

Note: Those conditions

will not apply if PSYNC/

PWRON2 are OTP disabled

PORB_MAIN: Main internal

supplies

(PWRON2_GATE_EN_OTP=

1 and PWRON2=1) and

(PSYNC=1&PSYNC_CFG_O

TP=1&PSYNC_EN_OTP=1)

FS_ENABLE=1

Unpowered

OFF Mode

-DS_Logic ON

-HVLDO @

config

PWRON1=1

PWRON1=0 (1ms)

or AutoRetry (if OTP

enable)

PWRON1=PWRON2=0

VPRE_fb_ov or

(VREGx_TSD)

All regulators OFF

(no power down sequence)

Fail-Safe logic OFF

Start autoretry timer if enable

Autoretry counter

+1 if enable

DFS=1 (Deep Fail-Safe request

from the FS state machine)

PORB_FS: FS

internal supplies

Fail-safe State Machine

MAIN State Machine

Fuse Loading

and

Debug Mode

Wake from

DEEP-FS

VDDOTP=0 and FS_READY=1 and

(PWRON2_GATE_EN_OTP=1&PWRON

2=1)&VPRE_AUTO_ON_OTP=0 or

(VPRE_AUTO_ON_OTP=1) or

(PSYNC=1&PSYNC_CFG_OTP=0&PSY

NC_EN_OTP=1)

VPRE

Power

SLOTs

Power UP

stop

STBY

timer

End PWR_DOWN

FS_ENABLE=0

VREGx PWR_DOWN

FS_READY=1

PORB_MAIN=1 and

VBOS > VBOS_UHV

End PWR_UP

STBY timer expired

(STBY_TIMER_G flag)

STBY

wake up

(STBY pin)

Reg disable <STBY_DISCH_OTP and

(VMON1 < STBY_DISCH_OTP if

EXT_STBY_DISCH_OTP=1)

OFF Mode

PWRON2 = 1

DSM_Enable = 1

(OTP) and

PWRON2 = 0 and

PWRON2_GATE

_EN_OTP=1

GoTo_OFF_Mode=1 (I2C)

or FS_READY=0

or (VALID_WD = PWRON1=PWRON2=0)

or (PSYNC_PWRON_DOWN_OTP=1

and PSYNC=0)

VALID_WD = (ABIST2 or

NORMAL_FS) and

!(WD_WINDOW[3:0]=0000) and

!WD_DIS_OTP

NORMAL_

VREGx

PWR_DOWN

(inverse slot

power up)

Deep Sleep

Mode

(Only HVLDO

enable)

Stand-by

Mode

(VPRE to PFM

mode)

From any

FS_state after

`INIT_FS'

(PWRON1 = 1 or

PWRON2 = 1)

VREGx

PWR_DOWN

(inverse slot

power up)

Stand-by

PWR_UP

(VPRE to PWM

mode)

Stand-by

PWR_DOWN

(start STBY

timer if

enable)

Figure 5. Functional state diagram

8.7 Functional device operation

The VR5510 device has two independent logic blocks. The Main state machine manages the power

management, Standby mode, Deep Sleep mode, and the power-on sources. The Fail-safe sate machine

manages entry into Standby and monitors power management and the MCU.

8.8 Main state machine

The VR5510 starts when VSUP > VSUP_UVH and PWRON1 > PWRON1VIH or PWRON2 > PWRON2VIH. VBOS

powers up first, followed by VPRE. OTP programming determines the power-up sequence for the remaining

regulators. When the power-up sequence is finished, the main state machine is in Normal_M mode, which is

the application running mode with all the regulators on. Depending on the OTP configuration, HVLDO can be

programmed to be the first regulator to start up.

The device can be put into Standby mode by toggling the STBY pin or by issuing an I2C command in

conjunction with toggling the STBY pin (refer to Section 8.16 "Standby mode entry" for further details). The

VR5510

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 2 October 2024

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