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VR5510 Datasheet(PDF) 67 Page - NXP Semiconductors

Part # VR5510
Description  Multi-output PMIC with SMPS and LDO
PDF  200 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

VR5510 Datasheet(HTML) 67 Page - NXP Semiconductors

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NXP Semiconductors
VR5510
Multi-output PMIC with SMPS and LDO
aaa-039396
FCCU by pair,
FCCU12_FLT_POL = 1
VR5510
FCCU
Interface
FCCU
NXP MCU
FCCU1
FCCU2
FCCU_ERR0
FCCU_ERR1
VDDIO
GND
22 kΩ
5.1 kΩ
FCCU by pair,
FCCU12_FLT_POL = 0
VR5510
FCCU
Interface
FCCU
NXP MCU
FCCU1
FCCU2
FCCU_ERR0
FCCU_ERR1
VDDIO
GND
5.1 kΩ
22 kΩ
Figure 36. FCCU connection
22.5.2 FCCU12 independent monitoring
When FCCU1 and/or FCCU2 are used independently, the FCCU inputs can monitor two different and
independent error signals. For each input, the polarity of the FCCU fault signal is configurable with the
FCCU1_FLT_POL and FCCU2_FLT_POL bits (FS_I_SAFE_INPUTS register) during the INIT_FS phase.
FCCU1_FLT_POL
FCCU1 polarity configuration
0 (default)
FCCU1 low level is a fault
1
FCCU1 high level is a fault
Reset condition
POR
FCCU2_FLT_POL
FCCU2_FLT_POL
0 (default)
FCCU2 low level is a fault
1
FCCU2 high level is a fault
Reset condition
POR
Table 54. FCCU12 polarity configuration
When an FCCU fault is detected, the Fail-safe reaction on RSTB and/or FS0B is configurable with the
FCCU1_FS_IMPACT and FCCU2_FS_IMPACT bits (FS_I_SAFE_INPUTS register) during the INIT_FS phase.
FCCU1_FS_IMPACT
FCCU1 impact on RSTB/FS0B
0
FS0B only is asserted
1 (default)
FS0B and RSTB are asserted
Reset condition
POR
FCCU2_FS_IMPACT
FCCU2 impact on RSTB/FS0B
0
FS0B only is asserted
1 (default)
FS0B and RSTB are asserted
Reset condition
POR
Table 55. FCCU12 impact configuration
VR5510
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 2 October 2024
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