VR5510 datasheet(71/200 Pages) NXP

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NXP Semiconductors

VR5510

Multi-output PMIC with SMPS and LDO

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TCOREMON_OV

VBUCK1 = VCOREMON = 0.75 V

VBUCK1 = VCOREMON = 0.8 V

I2C

FS_I_NOT_SVS

I2C

FS_I_SVS

VBUCK12_SVS

Figure 37. SVS principle

22.6.3 VDDIO monitoring

The VDDIO input pin can be connected to VPRE, LDO1, LDO2, LDO3, BUCK2, BUCK3, or an external

regulator. The regulator connected to VDDIO must be at 1.8 V or 3.3 V to be compatible with overvoltage

and undervoltage monitoring thresholds. Specifying which regulator is connected to VDDIO (and hence,

which regulator is turned off when an overvoltage detection occurs) is done by configuration settings in the

VDDIO_REG_ASSIGN_OTP[2:0] bit field (CFG_I2C_OTP register).

If an external regulator is connected to VDDIO, this regulator cannot be turned off, but the overvoltage flag is

reported to the MCU which can take appropriate action.

In all cases, the Fail-safe reaction on RSTB and/or FS0B is configured with the VDDIO_OV_FS_IMPACT[1:0]

and VDDIO_UV_FS_IMPACT[1:0] bitfields in the FS_I_OVUV_SAFE_REACTION1 register.

The Fail-safe VDDIO voltage (1.8 V or 3.3 V) can be set via the VDDIO_V_OTP bit (CFG_ 1_OTP register).

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bandgap_FS

VDDIOOVTH_OTP[3:0]

VDDIOUVTH_OTP[3:0]

VDDIO_V_OTP

VDDIO

Figure 38. VDDIO monitor principle

VDDIO_OV_FS_IMPACT[1:0]

VDDIO OV impact on RSTB/FS0B

No effect on RSTB and FS0B

Table 61. VDDIO FS impact configuration

VR5510

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Product data sheet

Rev. 7.0 — 2 October 2024

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VR5510 Datasheet(PDF) 71 Page - NXP Semiconductors