VR5510 datasheet(21/200 Pages) NXP

21 / 200 page

NXP Semiconductors

VR5510

Multi-output PMIC with SMPS and LDO

2. Deep Sleep mode:

Deep Sleep mode shuts down all VR5510 regulators except the HVLDO in LDO mode. The PWRON2 input

detector is active in Deep Sleep mode and can trigger a turn-on event.

The DSM_EN_OTP bit (DSM_EN_OTP register) enables or disables the Deep Sleep (DSM) mode of operation.

OTP description

Deep Sleep mode

DSM Disabled

DSM_EN_OTP

Enables or disables Deep Sleep mode of operation

DSM Enabled

Table 8. Deep Sleep mode OTP bit settings

When DS mode is enabled, the PWRON2 pin is used to transition to DSM mode from normal operation, in

which case, the PWRON2_DSM_EN bit (M_MODE register) should be enabled.

If Deep Sleep mode is enabled, the HVLDO cannot be assigned to a slot and always starts first on the power-up

sequence (before VPRE).

In Deep Sleep Mode, the HVLDO can be only use in LDO mode.

3. Standby mode:

Standby mode is a low-power mode used when the device is required to go into a minimal supply current mode

while maintaining minimal preset output voltages. Standby mode is entered by toggling the STBY pin when

conditions are programmed correctly with the STBY_EN_OTP bit (CFG_ VPRE_ 2_OTP register) and the

STBY_WINDOW_EN_OTP bit (CFG_ 2_OTP register).

The main regulators switched on during low-power Standby mode are VPRE and the HVLDO. VPRE is forced

to operate in PFM mode while the HVLDO operates in LDO mode. An option is available to operate other

regulators (except BOOST) as well, but the switchers are then forced to operate only in PFM.

The BUCKx_STBY_EN bit enables or disables the Buck regulators in Standby mode.

The LDOx_STBY bit enables or disables the LDOs in Standby mode.

The HVLDO_STBY bit enables or disables the LDOs in Standby mode.

Refer to AN12880 for more Standby mode examples and details.

4. Normal mode:

In Normal mode, the device operates with the regulators turned-on according to the preprogrammed settings.

The device stays in Normal mode until the processor requests a transition into Standby mode or Deep Sleep

mode. The device exits Normal mode and goes into OFF mode or Deep Fail-safe mode when an internal fault is

detected or an external fault is indicated by the processor.

9 Best of supply

9.1 Functional description

The VBOS regulator manages the best of supply from VSUP, VPRE, or VBOOST to efficiently provide a 5.0 V

output for the device's internal biasing. VBOS also supplies the VPRE high-side and low-side gate drivers and

the VBOOST low-side gate driver.

A VBOS undervoltage could result in the device not being fully functional. Consequently, VBOS_UVL detection

powers down the device

A VSUP_UV7 undervoltage threshold is used to enable the path from VSUP to VBOS when VSUP <

VSUP_UV7. This provides a low drop path from VSUP while VRPE is going low and when the device is

VR5510

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 2 October 2024

Document feedback

21 / 200

VR5510 Datasheet(PDF) 21 Page - NXP Semiconductors

VR5510 Datasheet(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL