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VR5510 Datasheet(PDF) 39 Page - NXP Semiconductors

Part # VR5510
Description  Multi-output PMIC with SMPS and LDO
PDF  200 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

VR5510 Datasheet(HTML) 39 Page - NXP Semiconductors

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NXP Semiconductors
VR5510
Multi-output PMIC with SMPS and LDO
VR5510 Power Calculator tool to recalculate the theoretical efficiency. The real efficiency must be verified by
measurement at the application level.
Ext. C and L
Cin
60
μF
ESR Cin
10
mΩ
Cout
44
μF
ESR Cout
10
mΩ
L coil
1
μH
DCR coil
30
mΩ
Int. MOSFET
HS_Rdson
135
mΩ
QH
0.5
nC
THS_sw
5
ns
GHS_drive
5
V
LS-Rdson
80
mΩ
QLS
0.5
nC
TLS_sw
5
ns
GLS_drive
5
V
Ibuck3 (A)
0
2.75
2.0
1.0
BUCK3 Efficiency vs Ibuck3
1.25
0.25
0.5
0.75
2.25
2.5
1.50
1.75
aaa-039378
80
70
90
100
60
85
75
95
65
3.3 V
2.3 V
1.2 V
Table 20. BUCK3 theoretical efficiency
14 Linear voltage regulator: LDO1
14.1 Functional description
LDO1 is a medium voltage linear regulator. The output voltage is configurable from 1.1 V to 5 V by OTP
through the LDO1V_OTP [2:0] bit field (CFG_ LDO_ ALL2_OTP register). A minimum voltage drop is required,
depending on the output current capability (0.5 V for 150 mA and 1 V for 400 mA). The LDO current capability is
linear with the voltage drop and can be estimated to I(mA) = 500 x VLDO1_DROP -100 for an intermediate voltage
drop between 0.5 V and 1 V.
Overcurrent detection and a thermal shutdown are implemented on LDO1 to protect the internal pass device.
VR5510
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 2 October 2024
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