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VR5510 Datasheet(PDF) 96 Page - NXP Semiconductors

Part # VR5510
Description  Multi-output PMIC with SMPS and LDO
PDF  200 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

VR5510 Datasheet(HTML) 96 Page - NXP Semiconductors

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NXP Semiconductors
VR5510
Multi-output PMIC with SMPS and LDO
00
50 V/μs
01
100 V/μs
10
300 V/μs - fast
11
500 V/μs - ultra fast
Reset condition
POR
Description
Force disable of VPRE pull down
0
No effect (VPRE pull down will be automatically controlled by the logic)
1
VPRE pull down is disabled
VPRE_
PLDWN_DIS
Reset condition
POR
Description
Enable of HVLDO
0
No effect (regulator remains in existing state)
1
Enable
HVLDOEN
Reset condition
POR
Description
Disable of HVLDO
0
No effect (regulator remains in existing state)
1
HVLDO Disable
HVLDODIS
Reset condition
POR
Description
VPRE High Side pull up slew rate control
00
130 mA typical drive capability - slow
01
260 mA typical drive capability - medium
10
520 mA typical drive capability - fast
11
900 mA typical drive capability - ultra fast
VPRESRHS_
MSB [1:0]
Reset condition
POR
Table 85. M_REG_CTRL2 register description...continued
25.6 M_REG_CTRL3 register
Return to Register Map
Bits
BIT23
BIT22
BIT21
BIT20
BIT19
BIT18
BIT17
BIT16
Write
0
LDO3
_STBY
0
LDO2
_STBY
0
LDO1
_STBY
0
HVLDO
_STBY
Read
RESERVED
LDO3
_STBY
RESERVED
LDO2
_STBY
RESERVED
LDO1
_STBY
RESERVED
HVLDO
_STBY
Reset
0
1
0
1
0
1
0
1
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
0
VPREV_
STBY
0
BUCK3_
STBY
0
BUCK2_
STBY
0
BUCK1_
STBY
VR5510
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 2 October 2024
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