2.0 Hardware Interface
RC96V24DP
Single Device Data/Modem Data Pump
2-6
D96V24DSA
Table 2-2. Hardware Interface Signal Definitions
Label
I/O Type
Signal/Definition
OVERHEAD SIGNALS
XTLI
IEOB
Crystal/Clock ln and Crystal Out. The DSP must be connected to an external crystal
circuit consisting of a 24.00014 MHz crystal and two capacitors. Alternatively, XTLI,
may be driven with a buffered clock (e.g., square wave generator) or a sine wave
oscillator.
RESET
ID
Reset. The active low RESET input resets the internal modem logic. Upon transition of
RESET from low-to-high, the DSP interface memory bits are set to the default values.
+5VD
PWR
+5V Digital Supply. +5V ±5% is required.
+5VA
PWR
+5V Analog Supply. +5V ±5% is required.
DGND
GND
Digital Ground.
DGND
GND
Analog Ground.
SERIAL INTERFACE
Five TTL-level hardware interface circuits implement a CCITT V.24-compatible serial
data interface with control signals provided through the DSP interface memory.
RDCLK
OA
Receive Data Clock. In synchronous mode, the modem outputs a Receive Data Clock
(RDCLK in the form of 50 ±1% duty cycle square wave. The low-to-high transitions of
this output coincide with the center of received data bits.
TDCLK
OA
Transmit Data Clock. In synchronous mode, the modem outputs a Transmit Data Clock
(TDCLK). The TDCLK clock frequency is data rate ±0.01% with a duty cycle of 50 ±1%.
XTCLK
IA
External Transmit Clock. In synchronous mode, an external transmit data clock input
(XTCLK) can be supplied.
RXD
OA
Received Data. The modem presents received serial data on the Received Data (RXD)
output and to the interface memory Receive Data Register (RBUFFER) in both serial and
parallel modes.
TXD
IA
Transmitted Data. The modem obtains serial data to be transmitted on the TXD input in
serial mode, or from the interface memory Transmit Data Register (TBUFFER) in
parallel mode. (See TPDM bit.)
PARALLEL MICROPROCESSOR INTERFACE
Address, data, control and interrupt hardware interface signals implement an 8086-
compatible parallel microprocessor interface to a host processor. This parallel interface
allows the host to change modem configuration, read or write channel and diagnostic
data, and supervise modem operation by writing control bits and reading status bits.
D0-D7
IA/OA
Data Lines. Eight bidirectional data lines (DO-D7) provide parallel transfer of data
between the host and the modem.
CS
IA
Chip Select. The active low Chip Select (CS) input enables parallel data transfer over
the microprocessor bus.
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