22 / 34 page
3.0 Software Interface
RC96V24DP
3.3 Interface Memory Bit Functions
Single Device Data/Modem Data Pump
3-2
D96V24DSA
Table 3-1. Interface Memory Map
Register
Function
Register
Address
(Hex)
Bit
7
6
5
4
3
2
1
0
Interrupt Handling
1F
NSIA
NCIA
–
NSIE
NEWS
NCIE
–
NEWC
1E
TDBIA
RDBIA
TDBIE
–
TDBE
RDBIE
–
RDBF
RAM Access,
Control and Status
1D
XACC
–
–
–
IOX
XCRD
XWT
XCR
1C
X RAM ADDRESS (XADD)
1B
YACC
–
–
–
–
YCRD
YWT
YCR
1A
Y RAM ADDRESS (YADD)
19
X RAM DATA MSB (XDAM)
18
X RAM DATA LSB (XDAL)
17
Y RAM DATA MSB (YDAM)
16
Y RAM DATA LSB (YDAL)
–
15
–––
––
––
–
–
14
–––
––
––
–
Control
13
TLVL
VOL
TXCLK
12
CONFIGURATION (CONF)
Transmit Data
Buffer
11
–––
––
––
TXP
10
TRANSMIT DATA BUFFER (TBUFFER)
Status
0F
RLSD
FED
CTS
DSR
RI
TM
SYNCD
FLAGS
0E
RTDET
BRKD
PE
FE
OE
SPEED
0D
–
PNDET
S1DET
SCR1
U1DET
SADET
–
–
0C
EDET
–
–
–
DTDIG
0B
TONEA
TONEB
TONEC
ATV25
ATBELL
PNSUC
DTDET
BEL103
0A
–––
––
––
CRCS
Control
09
NV25
CC
DTMF
ORG
LL
DATA
–
SLEEP
08
ASYNC
TPDM
–
DDIS
TRFZ
–
RTRN
RTS
07
RDLE
RDL
L2ACT
–
L3ACT
RB
RA
ABORT
06
BRKS
EXOS
PARSL
PEN
STB
WDSZ
05
–
–
–
TXSQ
CEQE
RCEQ
TXVOC
–
04
EQRES
SWRES
–
–
EQFZ
IFIX
AGCFZ
CRFZ
03
NRZIE
HDLC
SPLIT
–
ARC
SDIS
GTE
–
02
–––
––
––
–
Receive Data Buffer
01
–––
––
––
RXP
00
RECEIVE DATA BUFFER (RBUFFER)
Note:
‘ – ’ in the BIT columns indicates reserved for modem use only.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
