AD8312 datasheet(13/20 Pages) AD

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Data Sheet

AD8312

Rev. B | Page 13 of 20

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 22 shows the basic connections for measurement mode.

A supply voltage of 2.7 V to 5.5 V is required. The supply to the

VPOS pin should be decoupled with a low inductance 0.1 μF

surface-mount ceramic capacitor. A series resistor of about 10 Ω

may be added; this resistor slightly reduces the supply voltage to the

AD8312 (maximum current into the VPOS pin is approximately

5.7 mA). Its use should be avoided in applications where the power

supply voltage is very low (that is, 2.7 V). A series inductor

provides similar power supply filtering with minimal drop in

supply voltage.

AD8312

OPTIONAL

(SEE TEXT)

OPTIONAL

(SEE TEXT)

VOUT

RFIN

COMM

CFLT

VPOS

VOUT

VSET

INPUT

0.1

F

52.3



Figure 22. Basic Connections for Operation in Measurement Mode

The AD8312 has an internal input coupling capacitor. This

eliminates the need for external ac coupling. In this example, a

broadband input match is achieved by connecting a 52.3 Ω resistor

between RFIN and ground. This resistance combines with the

internal input impedance of approximately 3 kΩ to give an overall

broadband input resistance of 50 Ω. Several other coupling

methods are possible; these are described in the Input Coupling

Options section.

The measurement mode is selected by connecting VSET to VOUT,

which establishes a feedback path and sets the logarithmic slope to

its nominal value. The peak voltage range of the measurement

extends from −49 dBm to 0 dBm at 0.9 GHz and is only slightly

less at higher frequencies up to 2.5 GHz. At a slope of 21.0 mV/dB,

this would amount to an output span of 1.029 V. Figure 23 shows

the transfer function for VOUT at a supply voltage of 2.7 V and

an input frequency of 900 MHz.

The load resistance on VOUT should not be lower than 4 kΩ so

that the full-scale output can be generated with the limited available

current of 1 mA maximum. Figure 23 shows the logarithmic

conformance under the same conditions.

1.2

1.0

0.8

0.6

0.4

0.2

–60

–50

–40

–30

–20

–10

PIN (dBm)

–1

–2

–3

INTERCEPT

3dB DYNAMIC RANGE

1dB DYNAMIC RANGE

VS= 2.7V

RT = 52.3



Figure 23. VOUT and Logarithmic Conformance Error vs.

Input Level vs. Input Level at 900 MHz

TRANSFER FUNCTION IN TERMS OF SLOPE AND

INTERCEPT

The transfer function of the AD8312 is characterized in terms

of its slope and intercept. The logarithmic slope is defined as the

change in the RSSI output voltage for a 1 dB change at the input.

For the AD8312, the slope is nominally 20 mV/dB. Therefore, a

10 dB change at the input results in a change at the output of

approximately 200 mV. Figure 23 shows the range over which

the device maintains its constant slope. The dynamic range can

be defined as the range over which the error remains within a

certain band, usually ±1 dB or ±3 dB. In Figure 23, for example,

the ±1 dB dynamic range is approximately 51 dB (from −49 dBm

to +2 dBm).

The intercept is the point at which the extrapolated linear response

would intersect the horizontal axis (see Figure 23). Using the slope

and intercept, the output voltage can be calculated for any input

level within the specified input range by

)

(

SLOPE

VOUT







where:

VOUT is the demodulated and filtered RSSI output.

VSLOPE is the logarithmic slope, expressed in V/dB.

PIN is the input signal, expressed in decibels relative to some

reference level (dBm in this case).

PO is the logarithmic intercept, expressed in decibels relative to

the same reference level.

For example, at an input level of −27 dBm, the output voltage is

)]

dBm

(

dBm

[

020









VOUT

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