Over free-air temperature range and VDD = 1.4V to 5.5V for TA = -40°C to 125°C (unless otherwise noted); Typical

specifications are at TA = 25°C and VDD = 1.8V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tINIT

Initialization time after power-on

reset(6)

1

ms

tRESET

Reset Time(7)

General Call Reset

0.1

ms

(1)

For VDD above 3.6V, refer to the PSRDC specification to calculate the accuracy shift as a result of the power supply variation

(2)

Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.

(3)

Hysteresis is defined as the ability to reproduce a temperature reading as the temperature varies from room → hot

→room→cold→room. The temperatures used for this test are -40°C, 25°C, and 125°C.

(4)

Quiescent current between conversions

(5)

For best temperature measurement accuracy, it is recommended to avoid any serial bus traffice during active temperature conversion

(6)

From device power-on reset to start of temperature conversion

(7)

From General Call Reset command received to start of temperature conversion

6.6 Two-Wire Interface Timing

Over free-air temperature range and VDD = 1.4V to 5.5V for TA = -40 °C to 125 °C (unless otherwise noted)

STANDARD

FAST-MODE

FAST-MODE PLUS

UNIT

Min

Max

Min

Max

Min

Max

f(SCL)

SCL operating frequency

1

100

100

400

400

1000

kHz

t(BUF)

Bus-free time between STOP and START

conditions

4.7

1.3

0.5

µs

t(SUSTA)

Repeated START condition setup time

4.7

0.6

0.26

µs

t(HDSTA)

Hold time after repeated START condition.

After this period, the first clock is generated.

4.0

0.6

0.26

µs

t(SUSTO)

STOP condition setup time

4.0

0.6

0.26

µs

t(HDDAT)

Data hold time(1)

0

900

0

900

0

150

ns

t(SUDAT)

Data setup time

250

100

50

ns

t(LOW)

SCL clock low period

4.7

1.3

0.5

µs

t(HIGH)

SCL clock high period

4.0

0.6

0.26

µs

t(VDAT)

Data valid time (data response time)(2)

3.45

0.9

0.45

µs

tR

SDA, SCL rise time

1000

20

300

120

ns

tF

SDA, SCL fall time

300

300

120

ns

ttimeout

Timeout

30

30

30

ms

tLPF

Glitch suppression filter

50

50

50

ns

(1)

The maximum t( HDDAT) could be 0.9µs for Fast-Mode, and is less than the maximum t( VDAT) by a transition time.

(2)

t( VDAT) = time for data signal from SCL "LOW" to SDA output ("HIGH" to "LOW", depending on which is worse).

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TMP118

SNIS237 – DECEMBER 2024

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