Controller drives SDA

Target drives SDA

S

A6

A5

A4

A3

A2

A1

A0

0

A

0

0

0

0

P3

P2

P1

P0

A

D15

D14

D13

D12

D11

D10

D9

D8

A

D7

D6

D5

D4

D3

D2

D1

D0

A

P

START

R/W

ACK from Target

ACK from Target

ACK from Target

ACK from Target

STOP

Target Address

Register Pointer (N)

Data to Register N (MSB)

Data to Register N (LSB)

Figure 7-11. Write to Single Register

7.5.1.1.3.2 Reads

For a read operation the controller sends a START condition, followed by the target address with the R/W bit set

to 0b (signifying a write). The target acknowledges the write request, and the controller then sends the register

pointer in the next frame. The controller then initiates a START or RESTART followed by the target address with

the R/W bit set to 1b (signifying a read). A START initiates communication with an target, while a RESTART

allows the controller to access different registers on the same target without needing to send a full STOP signal

first. The controller continues to send out clock pulses but releases the SDA line so that the target can transmit

data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that

the controller is ready for more data. Once the controller has received the number of bytes the controller is

expecting, the controller sends a NACK, signaling to the target to halt communications and release the SDA line.

The controller follows this up with a STOP condition.

Note that:

• If the controller needs to read from the same register repeatedly, the controller is not required to resend the

pointer over and over again. The pointer value is stored in the device.

• The default pointer value upon device POR is 0h, so the controller can immediately proceed to read the

temperature result after device power-up without sending the pointer value for the Temp_Result register.

• Reading from a non-indexed register location returns 0x0h.

Figure 7-12 shows an example of reading a single word from a target register.

TMP118

SNIS237 – DECEMBER 2024

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