MAX8790 datasheet(9/24 Pages) MAXIM

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Six-String White LED Driver with Active

Current Balancing for LCD Panel Applications

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Pin Description (continued)

NAME

FUNCTION

FB6

LED String 6 Cathode Connection. FB6 is the open-drain output of an internal regulator, which controls

current through FB6. FB6 can sink up to 25mA. If unused, connect FB6 to GND.

Step-Up Controller Current-Sense Input. Connect the CS input to a ground-referenced sense resistor to

measure the current in the external MOSFET switch.

EXT

External MOSFET Gate-Drive Output

Overvoltage Sense. Connect OV to the center tap of a resistive voltage-divider from VOUT to ground. The

detection threshold for voltage limiting at OV is 1.23V (typ).

VCC

5V Linear Regulator Output. VCC provides power to the MAX8790 and is also used to bias the gate driver

for the external MOSFET. Bypass VCC to GND with a ceramic capacitor of 1µF or greater. If VIN is less

than or equal to 5.5V, connect VCC to IN to the disable the internal LDO and use the external 5V supply to

VCC. When SHDN is low, the internal linear regulator is disabled.

Supply Input. VIN biases the internal 5V linear regulator that powers the device. Bypass IN to GND directly

at the pin with a 0.1µF or greater ceramic capacitor.

CCV

Step-Up Converter Compensation Pin. Connect a 0.1µF ceramic capacitor and 1.2k

Ω resistor from CCV to

GND. When the MAX8790 shuts down, CCV is discharged to 0V through an internal 20k

Ω resistor.

ISET

Full-Scale LED Current Adjustment Pin. The resistance from ISET to GND controls the full-scale current in

each LED string:

ILEDmax = 20mA x 100k

Ω/RISET

The acceptable resistance range is 80k

Ω < RISET < 133kΩ, which corresponds to full-scale LED current of

25mA > ILEDmax > 15mA. Connect ISET to VCC for a default full-scale LED current of 20mA.

FSET

PLL Free-Running Frequency Control Pin. The resistance from FSET to GND controls the PLL oscillator’s

free-running frequency, fPLL:

fPLL = 1 / (10 x RFSET x 800pF)

The capture range is 0.6 x fPLL to fPLL. The acceptable resistance range for FSET is 250k

Ω < RFSET <

754k

Ω, which corresponds to a frequency range of 500Hz > fPLL > 166Hz. The resulting capture

frequency range is 100Hz to 500Hz.

CPLL

Phase-Locked Loop-Compensation Capacitor Pin. The capacitance at CPLL compensates the PLL loop

response. Connect a 0.1µF ceramic capacitor from CPLL to GND.

Exposed Backside Pad. Solder to the circuit board ground plane with sufficient copper connection to

ensure low thermal resistance. See the PCB Layout Guidelines section.

MAX8790 Datasheet(PDF) 9 Page - Maxim Integrated Products

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