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AD7147

Rev. 0 | Page 16 of 68

CDC CONVERSION SEQUENCE TIME

Table 10. CDC Conversion Times for Full Power Mode

Conversion Time (ms)

SEQUENCE_STAGE_NUM

Decimation = 64

Decimation = 128

Decimation = 256

0.768

1.536

3.072

1.536

3.072

6.144

2.304

4.608

9.216

3.072

6.144

12.288

3.84

7.68

15.36

4.608

9.216

18.432

5.376

10.752

21.504

6.144

12.288

24.576

6.912

13.824

27.648

7.68

15.36

30.72

8.448

16.896

33.792

9.216

18.432

36.864

The time required for the CDC to complete the measurement of

all 12 stages is defined as the CDC conversion sequence time. The

SEQUENCE_STAGE_NUM and DECIMATION bits determine

the conversion time, as listed in Table 10.

For example, if the device is operated with a decimation rate

of 128 and the SEQUENCE_STAGE_NUM bit is set to 5 for the

conversion of six stages in a sequence, the conversion sequence

time is 9.216 ms.

Full Power Mode CDC Conversion Sequence Time

The full power mode CDC conversion sequence time for all

12 stages is set by configuring the SEQUENCE_STAGE_NUM

and DECIMATION bits as outlined in Table 10.

Figure 26 shows a simplified timing diagram of the full power

mode CDC conversion time. The full power mode CDC con-

version time (tCONV_FP) is set using the values shown in Table 10.

CONVERSION

SEQUENCE N

CONVERSION

SEQUENCE N + 1

CONVERSION

SEQUENCE N + 2

CDC

CONVERSION

tCONV_FP

Figure 26. Full Power Mode CDC Conversion Sequence Time

Low Power Mode CDC Conversion Sequence Time

with Delay

The frequency of each CDC conversion while operating in the

low power automatic wake-up mode is controlled by using the

LP_CONV_DELAY bits located at Address 0x000 [3:2] in

addition to the registers listed in Table 10. This feature provides

some flexibility for optimizing the tradeoff between the conversion

time needed to meet system requirements and the power

consumption of the AD7147.

For example, maximum power savings is achieved when the

LP_CONV_DELAY bits are set to 11. With a setting of 11, the

AD7147 automatically wakes up, performing a conversion every

800 ms.

Table 11. LP_CONV_DELAY Settings

LP_CONV_DELAY Bits

Delay Between Conversions (ms)

200

400

600

800

Figure 27 shows a simplified timing example of the low power

mode CDC conversion time. As shown, the low power mode CDC

conversion time is set by tCONV_FP and the LP_CONV_DELAY bits.

CONVERSION

SEQUENCE N

CONVERSION

SEQUENCE N + 1

CDC

CONVERSION

LP_CONV_DELAY

tCONV_LP

tCONV_FP

Figure 27. Low Power Mode CDC Conversion Sequence Time

CDC CONVERSION RESULTS

Certain high resolution sensors require the host to read back the

CDC conversion results for processing. The registers required

for host processing are located in the Bank 3 registers. The host

processes the data read back from these registers using a software

algorithm in order to determine position information.

In addition to the results registers in the Bank 3 registers, the

AD7147 provides the 16-bit CDC output data directly, starting

at Address 0x00B of Bank 1. Reading back the CDC 16-bit

conversion data register allows for customer-specific application

data processing.

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