AD7147 datasheet(33/68 Pages) AD

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AD7147

Rev. 0 | Page 33 of 68

SDI

D15 D14

SCLK

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.

3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).

4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.

5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:

CW [15:11] = 11100 (ENABLE WORD)

CW [10] = 0 (R/W)

CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)

D15

DATA FOR STARTING

DATA FOR NEXT

D15

D14

234

910

ENABLE WORD

R/W

STARTING REGISTER ADDRESS

16-BIT COMMAND WORD

Figure 49. Sequential Register Write SPI Timing

SDI

16-BIT READBACK DATA

SCLK

XXX

SDO

XXX

D15

D14

D13

XXX

ENABLE WORD

R/W

16-BIT COMMAND WORD

NOTES

1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.

2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.

3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.

4. X DENOTES DON’T CARE.

5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.

6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.

7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:

CW [15:11] = 11100 (ENABLE WORD)

CW [10] = 1 (R/W)

CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)

Figure 50. Single Register Readback SPI Timing

Reading Data

A read transaction begins when the master writes the command

word to the AD7147 with the read/write bit set to 1. The master

then supplies 16 clock pulses per data-word to be read, and the

AD7147 clocks out data from the addressed register on the SDO

line. The first data-word is clocked out on the first falling edge

of SCLK following the command word, as shown in Figure 50.

The AD7147 continues to clock out data on the SDO line if the

master continues to supply the clock signal on SCLK. The read

transaction finishes when the master takes CS high. If the AD7147

address pointer reaches its maximum value, the AD7147 repeatedly

clocks out data from the addressed register. The address pointer

does not wrap around.

AD7147 Datasheet(PDF) 33 Page - Analog Devices

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