SC2542 datasheet(12/27 Pages) SEMTECH

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SC2542

POWER MANAGEMENT

pin high), an internal 84uA current source, Iss, (soft start

current) will charge the soft-start capacitor gradually. The

PWM output starts pulsing when the soft start voltage

reaches 1V.

This soft start scheme will ensure the duty cycle increases

slowly, therefore limiting the in rush current into the out-

put capacitor and also ensuring the inductor does not

saturate. The soft start capacitor will eventually be

charged up to 2.5V.

The soft-start sequence is initiated when EN pin or STBY

pin is high and Vcc > 5.5V or during recovery from a fault

condition ( OCP, OVP, or UVLO).

The period of start up can be programmed by the soft

start capacitor:

2.5

Shutdown

When the EN pin or STBY pin is pulled low, an internal

15uA current source discharges the soft-start capacitor

and DRVH/DRVL signals stop pulsing. The output volt-

age ramps down at a rate determined by the load condi-

tion.

The SC2542 can also be shutdown by pulling down di-

rectly on the SS pin. The designer needs to consider the

slope of the SS pin voltage and choose a suitable pull

down resistor to prevent the output from undershooting.

Shutdown can also be triggered under an OCP condition.

When an OCP condition is detected, DRVH and DRVL will

stop pulsing and enter a “tri-state shutdown” with the

output voltage ramping down at a rate determined by

the load condition. The internal 15uA current source will

begin discharging the soft-start capacitor and when the

soft-start voltage reaches 0.65V, DRVL will go high.

Over Current Protection (OCP)

The inductor current is sensed by using the low side

MOSFET Rds(on). After low side MOSFET is turned on,

the OCP comparator starts monitoring the voltage drop

across the MOSFET. The OCP trip level is programmed

by a resistor from the ILIM pin to the phase node. There

Applications Information (Cont.)

is an internal current source that flows out of the ILIM

pin which will generate a voltage drop on the setting resis-

tor. When the sum of the setting resistor voltage and

the MOSFET drain to source voltage is less then zero,

the OCP condition will be flagged. This functionality is

depicted in Figure 8.

The following formula is used to set the OCP level:

When OCP is tripped, both high side and low side MOS-

FETs will be turned off and this condition is latched. At

the same time, the soft start cap will be discharged by

the internal current source of 15uA. When the Vss drops

bellow 0.65V, the DRVL pin will go high again.

To avoid switching noise during the phase node commu-

tation, a 100nS blanking time is built in after the low

side MOSFET is turned on, as shown in Fig. 9.

10uA

OCP

DRVL

ILIM

Out

OUTPUT

VCC

DRVH

Figure 8. Block diagram of over current protection.

100nS

Blanking

OCP

100nS

Blanking

OCP

Figure 9. OCP comparator timing chart.

)

ILIM

PEAK

DS ON

µ ×=

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